Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Myers, Chris J. |
Other Author |
Belluomini, Wendy; Hofstee, H. Peter |
Title |
Verification of delayed-reset domino circuits using ATACS |
Date |
1999 |
Description |
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the self-resetting style since internally, a block of selfresetting or delayed-reset domino logic is asynchronous. The circuits are represented using timed event/level structures. These structures correspond very directly to gate level circuits, making the translation from a transistor schematic to a TEL structure straightforward. The statespace explosion problem is mitigated using an algorithm based on partially ordered sets (POSETs). Results on a number of circuits from the recently published guTS (gigahertz unit Test Site) processor from IBM indicate that modules of significant size can be verified with ATACS using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Language |
eng |
Bibliographic Citation |
Belluomini, W., Myers, C. J., & Hofstee, H. P. (1999). Verification of delayed-reset domino circuits using ATACS. The Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems. April. |
Rights Management |
(c) 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
143,094 bytes |
Identifier |
ir-main,15044 |
ARK |
ark:/87278/s6ks794w |
Setname |
ir_uspace |
ID |
706667 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6ks794w |