Direct synthesis of timed asynchronous circuits

This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. Our synthesis procedure begins with a deterministic signal transition graph specification to which timing constraints can be added. First, a timing analysis extracts the timed concurrency relation and timed causality relation between any two signal transitions. Then, a hazard-free implementation under the timing constraints is synthesized by constructing a precedence graph and finding a shortest path in the graph. Our method does not have the state explosion problem while the synthesized circuits have nearly the same area with the previous timed circuits.