Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Stevens, Kenneth |
Other Author |
Gebhardt, Daniel; You, Junbok; Lee, W. Scott |
Title |
Network simplicity for latency insensitive cores |
Date |
2008 |
Description |
In this paper we examine a latency insensitive net- work composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is compatible with this network, thus reducing adapter overhead and buffering needs by applying backpressure directly to the sending core. We show that under realistic traffic patterns our sample network meets performance requirements and uses less power compared to a similar design. This concept of a simplified network, along with latency insensitive cores lends itself well to meeting the needs of low-power interconnect components in future design processes. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
209 |
Last Page |
210 |
Language |
eng |
Bibliographic Citation |
Gebhardt, D., You, J., Lee, W. S. & Stevens, K. S. (2008). Network simplicity for latency insensitive cores. 2nd International Symposium on Network-on-Chip, 209-10. April. |
Rights Management |
(c) 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
172,375 bytes |
Identifier |
ir-main,15279 |
ARK |
ark:/87278/s69c7fws |
Setname |
ir_uspace |
ID |
705498 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s69c7fws |