Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Harrison, Reid R. |
Other Author |
Charles, C. |
Title |
Low-power low-noise CMOS amplifier for neural recording applications |
Date |
2003-06 |
Description |
There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit-the noise efficiency factor-for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5- m CMOS process, passes signals from 0.025 Hz to 7.2 kHz with an input-referred noise of 2.2 Vrms and a power dissipation of 80 W while consuming 0.16 mm2 of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 W while maintaining a similar noise-power tradeoff. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Journal Title |
IEEE Journal of Solid-State Circuits |
Volume |
38 |
Issue |
6 |
First Page |
958 |
Last Page |
965 |
DOI |
10.1109/JSSC.2003.811979 |
citatation_issn |
0018-9200 |
Subject |
Bioamplifier; Analog integrated circuits; Biosignal amplifier; Low noise; Low-power circuit design; Neural recordings; Neural amplifier; Noise efficiency factor; Subthreshold circuit design; Weak inversion |
Subject LCSH |
Metal oxide semiconductors; Integrated circuits; Microelectrodes; Implants, Artificial; Electroencephalography |
Language |
eng |
Bibliographic Citation |
Harrison, R. R., & Charles, C. (2003). Low-power low-noise CMOS amplifier for neural recording applications. EEE Journal of Solid-State Circuits, 38(6), 958-65. June. |
Rights Management |
(c) 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
656,242 bytes |
Identifier |
ir-main,13935 |
ARK |
ark:/87278/s68p6j6g |
Setname |
ir_uspace |
ID |
707183 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s68p6j6g |