Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Brunvand, Erik L. |
Other Author |
Yang, Jung-Lin |
Title |
Self-timed circuits using DCVSL semi-bundled delay wrappers |
Date |
2005 |
Description |
We present a technique for generating robust self-timed completion signals for general dynamic datapath circuits. The wrapper circuit is based on our previous domino semi-bundled delay (SBD) circuits, but uses DCVSL circuits in the wrapper for higher performance. We describe the basic SBD-DCVSL building blocks in the template with respect to their circuit structures and operational behavior. These DCVSL SBD circuits show better performance, exhibit reduced overhead, and require reduced operating margins for the matched delay compared with the domino version. The DCVSL wrapper can also identify a class of delay faults in the data path. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
441 |
Last Page |
444 |
Language |
eng |
Bibliographic Citation |
Yang, J.-L., & Brunvand, E. L. (2005). Self-timed circuits using DCVSL semi-bundled delay wrappers. International Symposium on Intelligent Signal Processing and Communication Systems, 441-4. ISPACS. December. |
Rights Management |
(c) 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
4,756,565 bytes |
Identifier |
ir-main,15729 |
ARK |
ark:/87278/s6r21jj6 |
Setname |
ir_uspace |
ID |
703286 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6r21jj6 |