Towards a verification technique for large synchronous circuits

We present a symbolic simulation based veri cation approach which can be applied to large synchronous circuits A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based veri cation approach e cient The constraints which are encoded through parametric Boolean expressions can involve the Boolean con nectives ???? ?? ?? the relational operators ?? ?? ?? ?? ?? ?? and logical connectives ?? This technique of using parametric Boolean expres sions vastly reduces the number of symbolic simulation vectors and the time for veri cation Our veri cation approach can also be applied for e cient modular veri cation of large designs the technique used is to verify each constituent sub module separately?? however in the context of the overall design Since regular arrays are part of many large designs?? we have developed an approach for the veri cation of regular arrays which combines formal veri cation at the high level and symbolic simulation at the low level e g ?? switch level We show the veri cation of a circuit called Minmax?? a pipelined cache memory system?? and an LRU array implementation of the least recently used block replacement policy?? to il lustrate our veri cation approach The experimental results are obtained using the COSMOS symbolic simulator