Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Brunvand, Erik L. |
Other Author |
Khoche, Ajay |
Title |
ACT: A DFT tool for self-timed circuits |
Date |
1997 |
Description |
This paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based selftimed circuits testable. The ACT tool is the first oFits kind for testing macro-module based self-timed circuits. ACT modifies designs automatically to incorporate partial scan and provides a complete path from schematic capturie to physical layout. It also has a test generation system to generate vectors for the testable design and to compute fault coverage of the generated tests. The test generatioin system includes a module for doing critical hazard free (.est generation using a new 6-valued algebra. ACT has been hilt around commercial tools from Viewlogic and Cascade. A Viewlogic schematic is used as the design entry point and Cascade tools are used for technology mapping. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
829 |
Last Page |
837 |
Language |
eng |
Bibliographic Citation |
Khoche, A., & Brunvand, E. L. (1997). ACT: A DFT tool for self-timed circuits. International Test Conference (ITC97), 829-37. |
Rights Management |
(c) 1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
692,943 bytes |
Identifier |
ir-main,15745 |
ARK |
ark:/87278/s64x5scd |
Setname |
ir_uspace |
ID |
706624 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s64x5scd |