| Publication Type |
technical report |
| School or College |
College of Engineering |
| Department |
Computing, School of |
| Creator |
Wolf, Thomas L. |
| Title |
The A3000: An asynchronous version of the R3000 |
| Date |
1995-03 |
| Description |
This thesis presents the architectural design and implementation of an N-stage Self-Timed RISC processor based on a subset of the MIPS R3000. The goal is to lay the ground work to show it will be possible in the future to build an asynchoronous pipelined RISC processor that has the chance to to commercially viable. As a step towards this goal, I describe the first implementation of the A3000. This processor is based on a popular commercial microprocessor, but is completely self-timed and is built without using vast amounts of silicon real estate or decades of design time. |
| Type |
Text |
| Publisher |
University of Utah |
| Subject |
A3000; asynchronous; computers |
| Subject LCSH |
RISC microprocessors; Asynchronous circuits;.Computer architecture |
| Language |
eng |
| Bibliographic Citation |
Wolf, T. L. (1995). The A3000: An asynchronous version of the R3000. |
| Series |
University of Utah Computer Science Technical Report |
| Relation is Part of |
ARPANET |
| Format Medium |
application/pdf |
| Format Extent |
195,052 Bytes |
| File Name |
Wolf-An_Asynchronous_Version.pdf |
| Conversion Specifications |
Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by Adobe Acrobat Pro X for CONTENTdm display |
| ARK |
ark:/87278/s6ns2v0f |
| Setname |
ir_computersa |
| ID |
93222 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6ns2v0f |
