Behavioral simulation from high-level specifications

A validation tool for synchronous hardware systems based on process composition and symbolic simulation has been developed. The problems addressed are:; • effective evaluation of a design through high-level simulation • quick exploration of alternative designs • contraction of the I/O vector space for simulators; • how to adapt solutions to the above problems for regular arrays; The simulation system is built around the Hardware Description Language HOP. HOP stands for Hardware viewed as Objects and Processes. It is a high-level language for specifying lockstep synchronous systems. It takes the view of interacting processes like CSP. Each module has ports that are channels for value communication and events that stand for control lines. Input and output events cause synchronization of modules. Input and output ports result in value communication between modules. Values are represented as abstract data types. This is; the framework around which the HOP simulation system operates.; In bottom up design, an architect often finds that the behavior of modules that comprise the system are clear but is interested in finding out the behavior of the system when they are all put together in different ways. PARCOMP, a tool for process composition infers the behavior of a collection of interacting processes. This provides the advantages of simplifying the behavior, detection of sequencing errors as well as speed up in simulation. PARCOMP deals with the explosion of control states by statically pruning away unreachable states. The I/O vector space of current simulators is enormous and users are forced to wade their ways through seas of bits. This vector space is condensed using symbolic simulation. The simulator inputs in symbolic simulation are variables that stand for all their instances and the output of the simulator is expressions in terms of those input variables. These expressions can be simplified using re-write rules.; Regular arrays are ubiquitous in VLSI. PARCOMP-DC, a divide and conquer version of PARCOMP infers the behavior of array structures. PARCOMP-DC takes as input, the specification of one module in the array and a recurrence relation that specifies the interconnections within the array. It produces a concise specification; of the entire array structure as its output.; The simulator is an architectural level simulator. Simulating at this level offers the advantages of quick verification of the design concept, capability to explore different designs quickly, faster simulation and early detection of design errors. Daemons, data driven procedures are used to watch ports of modules and collect; data during simulation.; The HOP simulation system has been implemented in FROBS, an object oriented frame language based on Lisp. Daemons and re-write rules are implemented using forward chaining rules. I feel that symbolic simulation and process composition greatly enhance the understanding of collective behavior of systems at a high level of abstraction. I believe that these ideas can be applied to other simulation systems as well.