Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Stevens, Kenneth |
Other Author |
Davis, Al; Coates, Bill |
Title |
The post office experience: designing a large asynchronous chip |
Date |
1993 |
Description |
The Post Office is an asynchronous, 300,000 transistor, full-custom CMOS chip designed as the communication component for the Mayfly scalable parallel processor. Performance requirements led to the development of a design style which permits the design of sequential circuits operating under a restricted form of multiple input change sign alling called burst-mode. The Post Office complexity forced us to develop a set of design fools capable of correctly synthesizing transistor circuits front state machine and equation specifications, and capable of verifying the correctness of the resultant circuity using implementation specific timing assumptions. The paper provides a case study of this design experience. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
409 |
Last Page |
418 |
Language |
eng |
Bibliographic Citation |
Stevens, K. S., Davis, A., & Coates, B. (1993). The post office experience: designing a large asynchronous chip. Proceedings of the 26th Hawaii International Conference on System Sciences, 409-18. January. |
Rights Management |
(c) 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
948,109 bytes |
Identifier |
ir-main,15316 |
ARK |
ark:/87278/s6zp4qp8 |
Setname |
ir_uspace |
ID |
706343 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6zp4qp8 |