Verification of regular arrays by symbolic simulation

Many algorithms have an efficient hardware formulation as a regular array of cells, which can be implemented in VLSI as regular circuit structures. Bit-sliced microprocessors, pattern matching circuits, associative cache memories, Hue-grain systolic arrays, and embedded memory-with-logic structures are representative of the regular array design style. In this paper, we illustrate a verification approach for regular arrays. Our approach for the verification of regular arrays combines formal verification at the high level and symbolic simulation at the low level(e.g., switch-level). The verification approach is based on a simple hardware specification formalism called HOP, a parallel composition algorithm for regular arrays called PCA, and a switch-level symbolic simulator (e.g., COSMOS). We illustrate our verification approach on the Least Recently Used(LRU) priority algorithm implemented as a two-dimensional array of LRU cells in VLSI. We also show a new technique of encoding input constraints as parametric boolean expressions on inputs to reduce the number of symbolic simulation vectors required for verification. The use of this technique in LRU array verification results in the simulation of only one symbolic simulation vector independent of the size of the LRU array.