| Publication Type |
pre-print |
| School or College |
College of Engineering |
| Department |
Electrical & Computer Engineering |
| Creator |
Stevens, Kenneth |
| Other Author |
Bhadra, Dipanjan; Vij, Vikas S. |
| Title |
A low power UART design based on asynchronous techniques |
| Date |
2013-01-01 |
| Description |
Abstract-Universal Asynchronous Receiver Transmitter (UART) implements serial communication between peripherals and remote embedded systems. The UART protocol is defined based on fixed frequencies with a sampling method to achieve robustness under reasonable frequency variations between systems. Such design specifications are natural for clocked domains. This work investigates whether this simple clocked hardware protocol can be advantageously implemented using asynchronous design techniques. A full duplex clocked and asynchronous UART are implemented and compared. The asynchronous design results in average power of about one fourth that of the clocked design under standard operating modes. |
| Type |
Text |
| Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
| First Page |
21 |
| Last Page |
24 |
| Language |
eng |
| Bibliographic Citation |
Bhadra, D., Vij, V. S., & Stevens, K. S. (2013). A low power UART design based on asynchronous techniques. Midwest Symposium on Circuits and Systems, 6674575, 21-4. |
| Rights Management |
(c) [Year] IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| Format Medium |
application/pdf |
| Format Extent |
683,245 bytes |
| Identifier |
uspace,18458 |
| ARK |
ark:/87278/s6zd1bxz |
| Setname |
ir_uspace |
| ID |
711951 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6zd1bxz |
