Low power PLL building blocks

In recent years integrated circuit power consumption has become one of the most important and critical performance specifications for a wide range of mobile, battery-operated devices. This dissertation addresses the significant power dissipation limitations imposed on a fully implantable wireless neural recording system in which power must be minimized to avoid cellular necrosis. Two core PLL circuits, the voltage-controlled oscillator (VCO) and multimodulus divider, have been developed in a 0.6-?m BiCMOS process technology with a power dissipation target of 4.5 mW with a typical output frequency of 915 MHz. To facilitate the development of a low power VCO, a novel integrated inductor design method is proposed to optimize inductors specifically for power dissipation. Such optimized inductors result in minimum operating currents up to 25 times lower than inductors optimized for Q.