TO
Filters: Subject: "Logic synthesis" Department: "Electrical & Computer Engineering" Collection: "ir_etd"
1 - 25 of 2
| Title | Setname | Type | ||
|---|---|---|---|---|
| 1 |
 |
Design and implementation of clocked open core protocol interfaces for intellectual property cores and on-chip network fabric | ir_etd | Text |
| 2 |
 |
Design automation for integrated optics | ir_etd | Text |
1 - 25 of 2