TO
1 - 25 of 3
| Author | Title | Subject | Date | Publication Type | ||
|---|---|---|---|---|---|---|
| 1 |
 |
Manoranjan, Jotham Vaddaboina | Relative timing based verification and design with delay insensitive signal path modeling with application for field programmable gate arrays | Applied sciences; Asynchronous circuits; FPGAs | 2017 | dissertation |
| 2 |
 |
Xu, Yang | Algorithms for automatic generation of relative timing constraints | Asynchronous circuits; formal verification; relative timing | 2011-05 | dissertation |
| 3 |
 |
Sai, Santosh Varanasi Naga | Performance analysis of four-phase untimed asynchronous handshake protocols | Asynchronous circuits | 2009-02-26 | thesis |
1 - 25 of 3