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Filters: Department: "Electrical & Computer Engineering" Collection: "ir_etd" Subject: "Verification"
1 - 25 of 2
| Author | Title | Subject | Date | Publication Type | ||
|---|---|---|---|---|---|---|
| 1 |
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Batchu, Satish | Automatic extraction of behavioral models from simulations of analog/mixed-signal (AMS) circuits | AMS; Analog/mixed-signal; Modeling; Petri-net; Simulation; Verification | 2011-05 | thesis |
| 2 |
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Desai, Krishnaji | Symbolic asynchronous hardware protocol verification for compositions with relative timing | BDD; Relative timing; SAT; Symbolic model checking; Timed asynchronous protocol; Verification | 2010 | thesis |
1 - 25 of 2