Energy-efficient design of an asynchronous network-on-chip

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Publication Type dissertation
School or College College of Engineering
Department Computer Science
Author Gebhardt, Daniel J.
Title Energy-efficient design of an asynchronous network-on-chip
Date 2011-08
Description Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy.
Type Text
Publisher University of Utah
Subject Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip
Dissertation Institution University of Utah
Dissertation Name Doctor of Philosophy
Language eng
Rights Management Copyright © Daniel J. Gebhardt 2011
Format Medium application/pdf
Format Extent 1,804,087 bytes
Identifier us-etd3,55865
Source Original housed in Marriott Library Special Collections, TK7.5 2011 .G46
ARK ark:/87278/s644626x
Setname ir_etd
Date Created 2012-04-24
Date Modified 2017-07-26
ID 194742
Reference URL https://collections.lib.utah.edu/ark:/87278/s644626x