A multiphase interpolating digital power amplifier for TX beamforming

C-2C, Split-array switched-capacitor power amplifier (SA-SCPA) are presented toovercome the challenges of simultaneously designing SCPAs with high resolution and high output power. Split-arrays allow a capacitance array to be subdivided with the aid of an attenuation capacitor, CA, to balance the charge between the arrays, regardless of the size of the arrays, or their associated capacitance. This allows a reduction in area and allows for array capacitance to be scaled to usable values for high resolution arrays. C-2C arrays are widely used because of the low ratio of the maximum-to-minimum capacitance, which allows for better capacitor matching, at the expense of sensitivity to parasitic effects. The size of the C-2C array increases linearly with the resolution, thus occupying less area then a binary-weighted array. The sizes of the capacitors are fixed and small, making the switches see approximately the same small capacitive load, thus easing the switch design as well as the layout, since the entire topology is composed of the replicas of a small C-2C block. Based on the SA-SCPA mentioned above, a multiphase interpolating digital power amplifier for TX beamforming is presented. This work consists of four key concepts. First, A 13b, 16-phase split-array multiphase SCPA (SAMP-SCPA) is fabricated, which is not just a power amplifier, but a versatile digital transmitter front-end. SAMP-SCPAs can achieve similar output power and system efficiency to prior art in digital PAs, while offering reduced OOB noise. Second, a fully-digital phased-array system that comprises 4 chains implemented as SAMP-SCPAs is fabricated, which can significantly improve the effective SNR at the output, when configured as a beamformer. Third, the phased-array implemented in SAMP-SCPA consists of a phase and amplitude decoder logic as a phase shifter and amplitude weight to precisely control the direction angle when steering a radio frequency beam, in a smaller area with lower losses than conventional digital phases-arrays, which can simply the whole circuit and reduce the power. Finally, the digital phased-array system can achieve high resolution when electronically steering the beam. Any necessary phase/amplitude shift can be added to the amplitude and phase modulation. A 4-element digital modulated multiphase phased-array TX in 65nm CMOS is designed and fabricated to demonstrate the prototype, which to my knowledge is the first of its kind. It can achieve < 1° phase resolution and <1 dB gain error with the 9-bit SAMP-SCPA while obtaining 24.4 dBm peak output power and 24% peak SE with no digital predistortion (DPD).

A MULTIPHASE INTERPOLATING DIGITAL POWER AMPLIFIER FOR TX BEAMFORMING by Zhidong Bai A dissertation submitted to the faculty of The University of Utah in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical and Computing Engineering The University of Utah May 2019 Copyright © Zhidong Bai 2019 All Rights Reserved The University of Utah Graduate School STATEMENT OF DISSERTATION APPROVAL The dissertation of Zhidong Bai has been approved by the following supervisory committee members: , Chair Jeffrey Sean Walling 2/22/2019 Date Approved , Member Behrouz Farhang 2/22/2019 Date Approved , Member Kenneth S. Stevens 2/22/2019 Date Approved , Member Ross M. Walker 2/22/2019 Date Approved , Member Sneha K. Kasera 2/22/2019 Date Approved and by Florian Solzbacher the Department/College/School of , Chair/Dean of Electrical and Computer Engineering and by David B. Kieda, Dean of The Graduate School. ABSTRACT C-2C, Split-array switched-capacitor power amplifier (SA-SCPA) are presented to overcome the challenges of simultaneously designing SCPAs with high resolution and high output power. Split-arrays allow a capacitance array to be subdivided with the aid of an attenuation capacitor, CA, to balance the charge between the arrays, regardless of the size of the arrays, or their associated capacitance. This allows a reduction in area and allows for array capacitance to be scaled to usable values for high resolution arrays. C-2C arrays are widely used because of the low ratio of the maximum-to-minimum capacitance, which allows for better capacitor matching, at the expense of sensitivity to parasitic effects. The size of the C-2C array increases linearly with the resolution, thus occupying less area then a binary-weighted array. The sizes of the capacitors are fixed and small, making the switches see approximately the same small capacitive load, thus easing the switch design as well as the layout, since the entire topology is composed of the replicas of a small C-2C block. Based on the SA-SCPA mentioned above, a multiphase interpolating digital power amplifier for TX beamforming is presented. This work consists of four key concepts. First, A 13b, 16-phase split-array multiphase SCPA (SAMP-SCPA) is fabricated, which is not just a power amplifier, but a versatile digital transmitter front-end. SAMP-SCPAs can achieve similar output power and system efficiency to prior art in digital PAs, while offering reduced OOB noise. Second, a fully-digital phased-array system that comprises 4 transmitter chains implemented as SAMP-SCPAs is fabricated, which can significantly improve the effective SNR at the output, when configured as a beamformer. Third, the phased-array implemented in SAMP-SCPA consists of a phase and amplitude decoder logic as a phase shifter and amplitude weight to precisely control the direction angle when steering a radio frequency beam, in a smaller area with lower losses than conventional digital phases-arrays, which can simply the whole circuit and reduce the power. Finally, the digital phased-array system can achieve high resolution when electronically steering the beam. Any necessary phase/amplitude shift can be added to the amplitude and phase modulation. A 4-element digital modulated multiphase phased-array TX in 65nm CMOS is designed and fabricated to demonstrate the prototype, which to my knowledge is the first of its kind. It can achieve < 1° phase resolution and <1 dB gain error with the 9-bit SAMPSCPA while obtaining 24.4 dBm peak output power and 24% peak SE with no digital predistortion (DPD). iv To my wife. To the world. TABLE OF CONTENTS ABSTRACT ....................................................................................................................... iii LIST OF TABLES ........................................................................................................... viii ACKNOWLEDGMENTS ................................................................................................. ix Chapters 1. INTRODUCTION .......................................................................................................... 1 1.1 Background and Motivation ................................................................................ 1 1.2 Contributions of This Research ........................................................................... 7 1.3 Dissertation Overview ......................................................................................... 8 2. CLASSIFICATION OF POWER AMPLIFIERS ......................................................... 12 2.1 Class-A, -B, -AB, and -C Power Amplifiers ..................................................... 12 2.2 Class-D Power Amplifier ................................................................................... 15 2.3 Class-E Power Amplifier ................................................................................... 17 2.4 Class-F Power Amplifier ................................................................................... 19 2.5 Inverse Class-F Power Amplifier...................................................................... 20 2.6 Inverse Class-D Power Amplifier ..................................................................... 21 2.7 Class-G Power Amplifier .................................................................................. 22 2.8 Summary ............................................................................................................ 23 3. LINEARIZATION TECHNIQUES.............................................................................. 34 3.1 Envelope Elimination and Restoration .............................................................. 35 3.2 Outphasing/LINC ............................................................................................... 37 3.3 Pulse-Width and Pulse-Position Modulation ..................................................... 38 3.4 Digital Polar PA ................................................................................................. 39 3.5 Quadrature Switching PA .................................................................................. 40 3.6 Summary ............................................................................................................ 41 4. PHASED ARRAY ARCHITECTURES ...................................................................... 46 4.1 Analog Phased Array ......................................................................................... 47 4.2 Digital Phased Array .......................................................................................... 51 4.3 Summary ............................................................................................................ 51 5. SPLIT-ARRAY, C-2C SWITCHED-CAPACITOR POWER AMPLIFIERS ............. 56 5.1 Introduction ........................................................................................................ 56 5.2 Theory of Operation ........................................................................................... 58 5.2.1 Conventional SCPA ............................................................................... 58 5.2.2 Operation of MP-SCPA ......................................................................... 61 5.2.3 Operation of SA-SCPA .......................................................................... 62 5.3 Resolution Limit of C-2C Array ........................................................................ 66 5.3.1 Nodal Parasitic ....................................................................................... 66 5.3.2 Mismatch................................................................................................ 67 5.4 Circuit Design Details ........................................................................................ 69 5.4.1 Top Level of the 13-b SAMP-SCPA ..................................................... 69 5.4.2 Unit Cell ................................................................................................. 70 5.4.3 Switch Driver Slice Design .................................................................... 71 5.4.4 Phase Selector and Amplitude Decoder Logic ...................................... 72 5.4.5 Matching Network ................................................................................. 73 5.5 Experimental Results ......................................................................................... 74 5.5.1 Static Measurements .............................................................................. 74 5.5.2 Dynamic Measurements......................................................................... 75 5.6 Summary ............................................................................................................ 76 6. A MULTIPHASE INTERPOLATING DIGITAL POWER AMPLIFIER FOR TX BEAMFORMING............................................................................................................. 92 6.1 Introduction ........................................................................................................ 92 6.2 Theoretical Operation of C-2C SA-SCPA ......................................................... 94 6.3 Multiphase Interpolation Beamforming ............................................................. 97 6.3.1 Number of Phase Selection in TX Beamforming .................................. 98 6.3.2 Operation of Multiphase Interpolation Beamforming ........................... 99 6.4 Circuit Design Details ...................................................................................... 101 6.4.1 Top Level of the 9-b SAMP-SCPA ..................................................... 102 6.4.2 Switch and Logic Design ..................................................................... 102 6.4.3 Switch Driver Slice Design .................................................................. 103 6.4.4 Phase Selector and Multiphase Decoder Logic ................................... 104 6.4.5 Matching Network ............................................................................... 104 6.5 Experimental Results ....................................................................................... 105 6.5.1 Static Measurements ............................................................................ 106 6.5.2 Dynamic Measurements....................................................................... 106 6.5.3 Beamforming Measurements ............................................................... 107 6.6 Summary .......................................................................................................... 107 7. CONCLUSIONS AND FUTURE WORK ................................................................. 123 REFERENCES ............................................................................................................... 125 vii LIST OF TABLES Tables 2.1. Conduction angles and duty cycles of linear PAs ...................................................... 33 2.2. Ideal peak efficiencies of linear PAs ......................................................................... 33 5.1. Comparison of prior art. ............................................................................................. 91 6.1. Power loss of different number of phases. ............................................................... 121 6.2. Comparison of prior art. ........................................................................................... 122 ACKNOWLEDGMENTS First of all, I would like to express my sincere appreciation to my advisor, Dr. Jeffrey Walling, for his invaluable support, encouragement, guidance of my Ph.D work for last 5 years. As an old Chinese saying goes “One day as your teacher, like a father for a lifetime.” I appreciate Dr. Walling’s assistance in my research, writing, and presentation. Without his help, my research could not be finished. It is my great honor to work with him. This experience has been a most valuable asset for my student career, and I will always cherish the memory. I would also like to express my appreciation to my Ph.D committee members: Dr. Behrouz Farhang, Dr. Ken Stevens, Dr. Ross Walker, and Dr. Sneha Kasera for their insightful comments and suggestions, which have helped me to make great progress in my research. I would like to thank my lab members in our lab, especially Wen Yuan for the instruction and assistance on the chip measurement. I also thank Ali Azam, who I have greatly enjoyed collaborating with over the last 5 years. I would also like to acknowledge the support of my parents. And finally, last but by no means least, I would like to acknowledge the support and love of my wife, Jiawei Wang. Her encouragement and support helps me to roll with the punches and to complete my research goal. Without her, this would not have been possible. CHAPTER 1 INTRODUCTION 1.1 Background and Motivation In recent years, there has been tremendous growth in research into radio frequency (RF) circuit design, driven largely by the advent of the cellular telephone and other forms of wireless communications. The first generation of cellular phone service was based on analog system transmissions, and it is known as 1G. Some of the most popular standards deployed for 1G system were AMPS (Advanced Mobile Phone Service), which was first launched in USA in 1980s. The next generation of cellular phone service (2G) was based on digital transmissions and included the standards D-AMPS (Digital AMPS), CDMA (Code Division Multiple Access), and GSM (Global System for Mobile Communications). The 2G carriers also began to offer additional services, such as paging, faxes, text messages, and voicemail. The third generation (3G) of cellular phone service, also known as UMTS (Universal Mobile Telecommunications Service), sustained higher data rates and open the way to Internet style applications. The 3G revolution allowed mobile telephone customers to use audio, graphics, and video applications, and UMTS delivers the first possibility of global roaming, with potential access to the Internet from any location. The current generation of cellular phone service, 4G has been developed with the aim of providing transmission rates up to 100Mbps. It is clear that it will require increased date rates as compared to 3G system. Long-Term Evolution (LTE) is a standard for high-speed 2 wireless communication for mobile phones and data terminals, based on the GSM and UMTS technologies, and applies more generally to the idea of improving wireless broadband speeds to meet increasing data rates. Also, driving the need for increased data rates in wireless communications systems are wireless local area network (WLAN) standards. The most prominent WLAN [1-3] standards are IEEE 802.11a, b, and g (also known as Wi-Fi). Personal wireless connectivity standards, such as Bluetooth [4-7] that allow users to achieve high data rates over short distances, have also grown in popularity. 5G will bring together evolved versions of existing radio-access, cloud, and core technologies with new complementary ones. Cellular networks will be able to serve many new use cases, as well as more traffic, devices, and types of devices, and even those with different operating requirements. Thus, 5G will bring much more than just performance enhancements. Our networked society is evolving, and the increasing number of uses for wireless networks plays an important role in this development. New wireless features will be introduced continuously throughout the development of 5G, as shown in Figure 1.1. The easiest way to accommodate the rising data rates required by new communications standards is to increase the bandwidth. This is often not possible, so engineers are forced to make the most of the limited bandwidth that is available. Even though some modulation schemes, such as OFDM (Orthogonal Frequency-Division Multiplexing), QAM (Quadrature Amplitude Modulation), etc., can increase data rates without affecting the bandwidth, the requirement for higher signal-to-noise (SNR) ratio is the limiting factor of these methods. One way to improve the SNR ratio is to simply use more power to transmit the signal, but this causes problems with battery life and is not effective in most modern wireless networks. As it becomes increasingly difficult to attain further improvements in data rates 3 through time and frequency domain methods, researchers are turning to spatial methods. Currently the most active spatial research area is multiple antenna system. While there are several ways in which multiple antennas can be exploited in a wireless system, the focus on this work is phased array applications. Phased arrays are capable of beamforming and electronic steering by adjusting the relative phases of the signal transmitted by each antenna. Future 5G communications will heavily leverage beamforming techniques, owing to the improvement in data transmission capacity. In a transmit (TX) beamformer, the phase and amplitude of an array of TXs can be arbitrarily adjusted to spatially steer a transmitted beam toward a user, or multiple users. The amplitude and direction of the beam is adjusted by controlling the gain and phase of each TX in the array. Gain is typically adjusted with a variable gain amplifier in the driver chain. The power amplifier (PA) continues to be the dominant energy consumer in most wireless transceivers. This is because a traditional linear amplifier must consume quiescent current regardless of the power that is delivered to the load (e.g., antenna). Modern highspeed wireless communications demand transmitter architectures that are simultaneously highly efficient and linear when amplifying signals with high peak-to-average power ratio (PAPR) signals and large output powers. Linear PAs in CMOS are inefficient when delivering high output powers since their efficiency is inversely proportional to their output power, as shown in Figure 1.2.[8], owing to low gain and losses in the output matching networks. Furthermore, they are also not linear due to parasitic and compression effects, meaning that they must be operated at significant output power backoff to meet fidelity specifications. Moreover, they also suffer from AM-AM and AM-PM distortion, as well as memory effect. To meet requirements on modulation standards such as adjacent channel leakage ratio (ACLR) and error-vector magnitude (EVM), self-testing circuitry is 4 implemented on-chip to adjust the input bias for different signal levels, known as analog predistortion (APD). An alternative technique is to modify the digital signal at base band, known as digital predistortion (DPD) [9-15]. Switching amplifiers [16-19] operate as polar transmitters (TX), combining the functions of a DAC, baseband filtering, frequency up-conversion, and amplification into a single block. They are more efficient than linear counterparts but must be linearized with external circuitry. Techniques such as envelope elimination and restoration (EER) [20-22], outphasing/Chireix [23-25], pulse-modulation [26], [27], and digital-Doherty [28-30] have been used, but in each case they rely on polar components of the nonconstant envelope modulated signal, which require high bandwidth amplitude and/or phase modulators [3133] that are difficult to produce in CMOS and also require significant static power consumption. The promising future of switching PAs is the development of RF CMOS processes. In the past, the CMOS scaling focused on faster switching and lower voltage. For PA applications, however, faster switching and higher voltage are preferred. As Moore’s law approaches its limit, it would be beneficial for the foundry to explore the RF friendly devices as the market for wireless communications grows rapidly. The efficiency of switching PAs is competitive but the peak output power is still limited by the lowoperating voltage, losses in the matching network due to low-Q on-chip inductors, and losses due to voltage/current division at the transistor drain node. The operating voltage can be increased by using cascoded switches [34]. An alternative way is to use off-chip inductors integrating surface mount (SMD) inductors at the packaging level. This will allow higher output power to be achieved without suffering matching losses as much. Digital power amplifiers (DPAs), shown in Figure 1.3, have provided a digital friendly means of amplifying nonconstant envelope modulation that interfaces directly 5 with digital signal processing. They can generally be broken down into polar and multiphase DPAs. However, their digital backend requires a modified implementation. As a result, switching PAs have not yet been prevalent in the market, due to the fact that both digital backend and PA output stage need to be designed in parallel to achieve good reliability. Polar DPAs [35-38] are problematic for two primary reasons. First, the polar signals (e.g., amplitude and phase modulation) have significantly wider bandwidth relative to the RF signal bandwidth. Second, the group delay of the amplitude- and phasemodulated signals is different, owing to the differing propagation frequency [39]. Alternatively, Cartesian architectures require multidimensional inputs, and owing to bondwire inductance and memory effects, the output can have a nonlinear transfer function that is dependent on the combination of the multidimensional input signal [31], [32], [40]. Additionally, Cartesian PAs have the disadvantage of lower peak output power, owing to out-of-phase (OOP) summation of the in-phase and quadrature signals. Multiphase amplifiers have been developed that reduce the losses due to OOP summation and do not require wideband phase modulators. In recent years, quadrature [31-33] and multiphase [41] digital PAs have been proposed. Quadrature- and multiphase- SCPAs (Q-SCPA and MP-SCPA, respectively) reduce the challenges associated with polar conversion and modulation [33], [41], while leveraging the other benefits of the SCPA. They do not suffer the same systematic nonlinearities as polar TXs, but they do suffer from reduction in output amplitude when compared to polar systems [42]. The Q-SCPA is a special case of the MP-SCPA, where the number of phases, M, is equal to 4. Q-SCPAs have a phase-dependent power drop caused by the 90-degree phase difference of the I and Q signals. Additional basis phases can be used to decrease the phase difference (e.g., increase constructive summation). Still, 6 the critical challenge for prior SCPA designs is their output resolution limiting the OOB noise. The minimum available size of a capacitor in each CMOS process and the associated matching due to process, voltage, and temperature (PVT) variations determine the maximum resolution of prior SCPAs. Split-array SCPAs (SA-SCPA) [43], [44] are introduced to overcome the challenges of simultaneously designing SCPAs with high resolution and high output power. Split-arrays (Figure 1.4a) allow a capacitance array to be subdivided with the aid of an attenuation capacitor, CA, to balance the charge between the arrays, regardless of the size of the arrays, or their associated capacitance. This allows a reduction in the area and allows for array capacitance to be scaled to usable values for high resolution arrays. The LSB subarray capacitance, in series with the capacitance from C A presents the equivalent of a unit capacitance in the MSB subarray. More than one split can be added to an array, but linearity is sensitive to matching and parasitic effects from CA. C-2C arrays are widely used because of the low ratio of the maximum-to-minimum capacitance, which allows for better capacitor matching [45], at the expense of sensitivity to parasitic effects [46], [47]. The size of the C-2C array increases linearly with the resolution, thus occupying less area then a binary-weighted array. The sizes of the capacitors are fixed and small, making the switches see approximately the same small capacitive load, thus easing the switch design as well as the layout, since the entire topology is composed of the replicas of a small C-2C block. In recent beamforming TXs, four primary means to control the output beam angle have been leveraged. Passive RF phase shifting is bulky and lossy, owing to high losses in the passive elements, and it is difficult to provide phase control through 360°. LO phase shifting often uses a single passive phase shifter, or a multiphase ring oscillator; these 7 typically provide lower phase resolution. Digitally controlled delay lines provide a wider bandwidth response but suffer from reduced phase resolution as frequency is increased and can consume high power [48]. Digital phase shifting techniques have recently shown promise in polar systems [49], [50] but the quadrature modulator typically used for phase shifting incurs high loss if placed directly at the output stage. 1.2 Contributions of This Research I propose a multiphase controller to directly control a PA allowing for high phase/gain resolution with reduced loss by performing a vector addition of the beam phase and amplitude. Such a scheme has been used recently to provide amplitude and phase modulation of the data [41]. The proposed work consists of three key concepts. First, I propose a split-array multiphase SCPA (SAMP-SCPA), which is not just a power amplifier, but a versatile digital transmitter front-end. SAMP-SCPAs can achieve similar output power and system efficiency to prior art in DPAs, while offering reduced OOB noise. Second, I propose a fully-digital phased-array system, which is comprised four transmitter chains implemented as SAMP-SCPAs. Phased arrays and MIMO systems can leverage spatial diversity or SNR enhancements to increase wireless channel capacity. Third, I propose a unique digital logic decoder as a phase shifter to precisely control the beam angle of the array. This replaces prior art in beamforming control and can simply the whole circuit and reduce the power. The digital phased-array proposed can achieve angular resolutions of less than 0.7° due to the accuracy of the aforementioned circuits and systems. Any necessary phase/amplitude shift for the array can be added in the digital domain to the amplitude and phase modulation. Hence, the work I propose allows for beamforming operation at higher efficiency and linearity and provides more flexibility to transmit the 8 signal directionally to any point in space. To my knowledge, the fully-digital phased-array system I propose is the first of this kind. 1.3 Dissertation Overview The dissertation is organized as follows: A review of different classes of power amplifiers is presented in Chapter 2. In Chapter 3, various conventional linearization techniques are reviewed, and their advantages and limitations are compared and discussed. After that, several linearization architectures are proposed, investigated, and demonstrated that address primary concerns with prior art in switching PA linearization. Chapter 4 provides an introduction of the different types of multiple antenna systems, with a focus on phased arrays, which are the target application of this work. In Chapter 5, I present a 13b C-2C SAMP-SCPA implemented in 65 nm CMOS. The SAMP-SCPA was designed for 16b resolution to offer extra states for linearization/calibration using DPD. Resolution limits for split-array SCPAs are presented. The SAMP-SCPA allows for the improvement of the SCPA resolution while minimizing the impact on the input power required to drive it. A prototype SAMP-SCPA, occupying 0.85 mm×2 mm, delivers a peak output power of 24 dBm with a peak system efficiency (SE) of 40% at 1.8 GHz. When amplifying a long-term evolution (LTE) signal, the average output power and SE are 18.8 dBm and 21.6%, respectively, with an adjacent channel leakage ration (ACLR) < -30 dBc and error vector magnitude (EVM) of 2.65 %-rms. The increased resolution allows output power to be traded off for improved linearity and a low power mode demonstrates an EVM as low as 1.0 %-rms. In Chapter 6, a 4-channel beamforming TX and implemented in 65nm CMOS is 9 presented. Each beamforming TX is comprised of a C-2C split-array multiphase switchedcapacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam-steering, and this SCPA is ideal for beamforming due to its high linearity, high output power and system efficiency (SE), and compact circuit size. A prototype 4element beamforming TX, occupying 2 mm×2.5 mm, are able to achieve peak output power of 24.4 dBm with a peak SE of 24%, while achieving < 1° phase resolution and <1 dB gain error. When transmitting a 15 MHz, 64 QAM long-term evolution (LTE) signal, it outputs 18.4 dBm at 14% SE with a measured adjacent channel leakage ratio (ACLR) < -30 dBc and error vector magnitude (EVM) of 3.27 %-rms at 1.75 GHz. The conclusions of this dissertation are summarized in Chapter 7. 10 Figure 1.1. Cellular generation evolution. Figure 1.2. Plot of PDF for 802.11 and efficiency of PAs (class-B and class-E) as a function of envelope. 11 Figure 1.3. Block diagram of a transmitter with a switching PA. Figure 1.4. Split-array SCPA schematics: (a) traditional binary/unary split-array; (b) C2C/unary split-array. CHAPTER 2 CLASSIFICATION OF POWER AMPLIFIERS The different power amplifier architectures can be grouped into two categories. The first category is transconductor based, such as class A, B, AB, and C. They are so-called linear PAs as the active device is acting as a voltage dependent current source. The second category is switching type, such as class -D, -E, -F, -D-1, -F-1, and -G, the transistor acts as a switch. Therefore, there is either zero voltage or zero current across the switch simultaneously, resulting a zero voltage-current product during a whole period, which can achieve high power efficiency. However, their output amplitudes are constant, so linearization techniques are required. In this chapter, linear PAs will be discussed followed by switching PAs. 2.1 Class-A, -B, -AB, and -C Power Amplifiers A generic configuration for a linear PA is shown in Figure 2.1. The RF choke acts as a current source and provides a DC path from the supply to bias the transistor. The only difference for different types of linear PAs is the bias point of the PA so that the conduction angles are different. Therefore, the duty cycles of different types of linear PA are summarized in Table 2.1 according to the conduction angles. The class-A PA operates linearly across the full input and output range. It is biased to be fully “on” during each cycle, and the corresponding conduction angle is 2π so that it 13 is at the exact midpoint of the voltage and current swing ranges. Though class-A has a high linearity, it suffers from low efficiency due to quiescent drain current. To calculate the maximum drain efficiency of class-A PAs, we note that if the drain voltage in Figure 2.1 is a sinusoid having a peak-to-peak voltage of approximately2𝑉𝐷𝐷 , then the power delivered to the matching network can be easily calculated as the product of the RMS voltage and current in the load: 𝑃𝑜𝑢𝑡 = 2 𝑖0𝑢𝑡 𝑅𝑜𝑝𝑡 2 = 2 𝑉0𝑢𝑡 2𝑅𝑜𝑝𝑡 = 2 𝑉𝐷𝐷 2𝑅𝑜𝑝𝑡 . (2.1) We notice that the bias voltage should be chosen so that the output swing is not clipped, regardless of the output amplitude, thus 𝑉𝐷𝐶 = 𝑉𝐷𝐷 . Using the same way, in order to make sure the device never stops conducting, the DC bias current must be large enough, regardless of the output amplitude, thus 𝐼𝐷𝐶 = 𝐼𝑜𝑢𝑡 . Therefore, 𝑅𝑜𝑝𝑡 can be represented as following: 𝑅𝑜𝑝𝑡 = 𝑉𝑜𝑢𝑡,𝑚𝑎𝑥 𝐼𝑜𝑢𝑡,𝑚𝑎𝑥 = 2𝑉𝐷𝐷 2𝐼𝐷𝐶 = 𝑉𝐷𝐷 𝐼𝐷𝐶 . (2.2) Since the RF choke current is relatively constant, the DC power drawn from the supply is the product of the DC current and DC supply voltage, using the (2.2), the DC power is given by 𝑉 𝑃𝐷𝐶 = 𝐼𝐷𝐶 𝑉𝐷𝐷 = 𝑉𝐷𝐷 𝑅 𝐷𝐷 = 𝑜𝑝𝑡 2 𝑉𝐷𝐷 𝑅𝑜𝑝𝑡 . (2.3) Thus, the maximum drain efficiency of the class-A PA is given by 𝜂= 𝑃𝑜𝑢𝑡 𝑃𝐷𝐶 == 2 1 𝑉𝐷𝐷 2 2 𝑉𝐷𝐷 = 50%. (2.4) The peak drain efficiency is 50% only if substantial nonlinearity is acceptable. Note that the output stage dissipates maximum power when the RF input signal is zero if achieving peak drain efficiency. Therefore, this result is only for an ideal class-A PA, regardless of 14 the loss in both active and passive devices and also the loss in the matching network. In practical design, the peak efficiency is usually less than 25%. Class-B PA is more efficient than ordinary Class-A configurations because of the drain voltage reaching maximum when the drain current is reduced to zero. In a Class-B PA, the transistor is biased to make sure it only conducts current for half of every conduction cycle. As seen from Figure 2.2, power is only dissipated when the device is on. Since power dissipated in the transistor is voltage times current, a net power saving is realized. Class-B PA requires substantial variation in the bias currents of the transistors in order to achieve the maximum efficiency, thereby facing severe linearity issues. In general, push-pull output stages are used to regain some linearity. The push-pull configuration is commonly employed in high performance audio power amplifiers because it can be embedded in a high gain feedback loop so as to minimize the distortion. In the RF range, on the other hand, it is difficult to achieve the same effect because a high loop gain typically necessitates multiple stages, leading to serious stability problems. The maximum output power for a Class-B PA is the same as (2.1). The average supply current is found by integrating the drain current over one period: 𝐼𝑑𝑐 = 2 𝑇/2 𝑉𝐷𝐷 ∫ 𝑅 𝑠𝑖𝑛𝜔𝑡𝑑𝑡 𝑇 0 𝑜𝑝𝑡 2𝑉 = 𝜋𝑅𝐷𝐷 . (2.5) 𝑜𝑝𝑡 The DC power is given by the product of the average supply current and the average supply voltage, which is given by 2𝑉 𝑃𝐷𝐶 = 𝐼𝐷𝐶 𝑉𝐷𝐷 = 𝑉𝐷𝐷 𝜋𝑅𝐷𝐷 = 𝑜𝑝𝑡 2 2𝑉𝐷𝐷 𝜋𝑅𝑜𝑝𝑡 . (2.6) Efficiency can be calculated as the output power divided by the DC power consumption: 𝜂= 𝑃𝑜𝑢𝑡 𝑃𝐷𝐶 == 2 𝜋 𝑉𝐷𝐷 2 4 𝑉𝐷𝐷 = 78.5%. (2.7) 15 The same considerations for nonideal efficiency still apply to this type of PA as did for the class-A PA. Note that this derivation assumes matching network exhibits no loss. Class-AB PA is biased between class-A and class-B states so that the efficiency is between the class-A and class-B PA. This type of PA is widely used in high speed communications due to a nice tradeoff between linearity and efficiency. Class-C PA is designed for further increasing the efficiency but with worse linearity, and it conducts for less than 50 % of each cycle. Unlike class-A or class-B designs, class-C has very high harmonic levels relative to the fundamental frequency. In this case, output matching network design is important to lower these unwanted signals to acceptable levels. As the conduction angle decreases, the transistor is on for a smaller fraction of the period, thus dissipating less power. Figure 2.2 shows the drain current for class-A, -B, -AB, and –C, respectively, and Table 2.2 summarized peak efficiencies for those PAs. 2.2 Class-D Power Amplifier In a typical Class-D power amplifier [51], a pair of transistors act as switches to generate a square wave output voltage and the current can only flow into the output at the fundamental frequency, shown in Figure 2.3. The PMOS and NMOS turns on alternately to generate a square wave at the drain. As shown in Figure 2.4 of the voltage and current waveforms for an ideal class-D PA, the PMOS is on during the positive half cycles, while the NMOS is on during the negative half cycles. This type of PA has a significant improvement in efficiency compared with linear PAs because of limiting the period over which the voltage and current waveforms are simultaneously nonzero. When the PMOS switch is closed, the drain is tied to 𝑉𝐷𝐷 , while the NMOS switch 16 is closed, the drain is tied to ground. Therefore, the amplitude of the output signal at the drain is the fundamental component of a square wave with the range from 𝑉𝐷𝐷 to ground, and it can be given by the first term in the Fourier expansion: 𝑉𝑜𝑢𝑡 = 2𝑉𝐷𝐷 𝜋 . (2.8) The output power can be expressed using the output voltage which is given by 𝑉2 𝑃𝑜𝑢𝑡 = 2𝑅𝑜𝑢𝑡 = 𝑜𝑝𝑡 2 2𝑉𝐷𝐷 𝜋 2 𝑅𝑜𝑝𝑡 . (2.9) Therefore, the output current can be expressed easily by using Ohm’s law: 𝑉 𝐼𝑜𝑢𝑡 = 𝑅𝑜𝑢𝑡 = 𝑜𝑝𝑡 2𝑉𝐷𝐷 𝜋𝑅𝑜𝑝𝑡 . (2.10) The DC current from the supply is equal to the average of the current passing through the PMOS, which is given by 𝐼𝐷𝐶 = 1 2𝜋 ∫ 𝐼𝑜𝑢𝑡 𝑠𝑖𝑛𝜔𝑡𝑑𝜔𝑡 2𝜋 𝜋 = 𝐼𝑜𝑢𝑡 𝜋 = 2𝑉𝐷𝐷 𝜋 2 𝑅𝑜𝑝𝑡 . (2.11) The DC power is given by 𝑃𝐷𝐶 = 𝐼𝐷𝐶 𝑉𝐷𝐶 = 2 2𝑉𝐷𝐷 𝜋 2 𝑅𝑜𝑝𝑡 . (2.12) From the above expressions, it is obvious that the efficiency of the ideal class-D PA can be 100%. In practical design, the finite transistor on-resistances and transistor switching times quickly degrade the performance of these amplifiers though. Moreover, there will be always a small overlap between conduction cycles of the two switches when both of them are on especially at high frequency. This leads to crowbar current flowing between the switches and potentially significant power consumption. In order to minimize the crowbar current, a nonoverlapping clock signal can be implemented so that there is a dead time when neither switch is on. In addition, drain capacitances are not a part of the tuned output network and result in these capacitances being charged and discharged 17 through the finite on-resistance of each transistor. Therefore, energy is dissipated whenever these drain capacitances are charged and discharged especially at high frequency. Furthermore, the efficiency will reduce drastically if there is any mismatch between the two devices used. The asymmetric switching can cause both transistors to be turned on at the same time. 2.3 Class-E Power Amplifier Class-E [52-54] PA, shown in Figure 2.5, is another type of switching PA using a different approach to insure that there is no overlap between drain voltage and current, and the transistor is operated as a switch like Class-D PA. In either case, the drain parasitic capacitance is usually detrimental. Unlike Class-D PA, the parasitic capacitance at the drain can be absorbed by reactive components. Figure 2.6 shows the waveforms at the drain of the transistor for an ideal class-E PA, which satisfies three conditions. The first condition is that 𝑉𝐷 remains low long enough for the current to drop to zero as the switch turns off. This condition is guaranteed by parasitic capacitance 𝐶𝐷 at the drain to resolve the issue of finite fail time at the gate of the transistor. If there is no 𝐶𝐷 , 𝑉𝐷 rises as 𝑉𝑖𝑛 drops, which will introduce substantial power loss in transistor. The second condition is that 𝑉𝐷 reaches zero just before the switch turns on, which can ensure that the voltage across and the current through the switch do not overlap in the vicinity of the turn-on point. Therefore, the power loss in the transistor will be minimized even with finite input and output transition times. The third condition is that the derivation of the voltage with respect to time is also near zero when the switch turns on, which reduce the sensitivity of the efficiency to violations of the second condition. If components or supply voltage variations introduce some overlap between the voltage 18 and current waveforms, the efficiency degrades only slightly. Therefore, the efficiency of ideal class-E PA can achieve 100%. The detailed derivation of the class-E PA design equations is discussed in [54]. The important equations are summarized in below. The output power delivered to the load is given by 𝑃𝑜𝑢𝑡 = 1 1+ 𝜋2 4 2 𝑉𝐷𝐷 𝑅𝑜𝑝𝑡 2 0.577𝑉𝐷𝐷 ≈ 𝑅𝑜𝑝𝑡 . (2.13) In order to find the optimal parameters, a desired output power can be calculated by 𝑉2 𝑅𝑜𝑝𝑡 = 0.577 𝑃𝐷𝐷 (2.14) 𝑋𝑜𝑝𝑡 = 1.1525𝑅𝑜𝑝𝑡 . (2.15) 𝑜𝑝𝑡 The shunt capacitance at the drain of the transistor represents a net susceptance, which may be realized with an explicit capacitor or with a parallel sum of capacitors, parasitic, and inductances. The value of susceptance is given by the following: 𝐵𝑜𝑢𝑡 = 0.1836 𝑃𝑜𝑝𝑡 . (2.16) The values of other components in Figure 2.5 is given by 𝐶𝐷 = 2 1 𝜋2 𝜋(1+ ) 𝜔𝑅𝑜𝑝𝑡 4 𝐿= 𝐿0 = ≈ 0.1836 𝜔𝑅𝑜𝑝𝑡 1.1525𝑅𝑜𝑝𝑡 𝜔 (𝑄−1.1525𝑅𝑜𝑝𝑡 ) 𝜔 1 𝐶0 = 𝜔2 𝐿 0 (2.17) (2.18) (2.19) (2.20) where ω is the center frequency, and 𝑄 is the quality factor of the matching network. ClassE PA exhibits a trade-off between efficiency and output harmonic content. For low 19 harmonic distortion, the 𝑄 of the output network must be higher than that typically required by the second and third condition. Additional filtering can precede the load resistor, but at the cost of power loss in the filter [55]. As a result, the class-E PA is a promising candidate for CMOS RF applications. The drain voltage can be reduced with proper cascades by replacing the RF choke with a finite inductor resonating with 𝐶𝐷 [56]. 2.4 Class-F Power Amplifier Class-F PAs [57-59] are another type of switching PA for improving the RF amplifier efficiency. The general configuration for it can be seen in Figure 2.7. Class-F PA uses an additional resonant network placed in the bias circuit to improve overall efficiency, which is achieved by providing proper harmonic terminations for many or all of the harmonics other than the fundamental. Therefore, the load matching passes all even harmonics as a short circuit and blocks all odd harmonics as an open circuit to avoid the voltage and current overlap at the drain of the transistor. As shown in Figure 2.7, the transmission line shows a large impedance close to infinity since the effective load resistance is close to zero at all odd harmonics. While at even harmonics, the transmission line becomes some multiple of half-wavelength and acts as a short circuit to ground. Therefore, the square voltage waveform and a half-rectified current waveform at the drain is shown in Figure 2.8. The amplitude of the square wave at the drain is 𝑉𝐷𝐷 with an input square wave. Therefore, the output voltage is the fundamental term of the Fourier expansion of the drain voltage waveform, so the output voltage is given by 20 𝑉𝑜𝑢𝑡 = 4𝑉𝐷𝐷 (2.21) 𝜋 The fundamental output current and DC current can be given by 𝐼𝑜𝑢𝑡,𝑓𝑢𝑛𝑑 = 𝐼𝐷𝐶 = 1 1 𝜋 ∫ 𝐼 𝑠𝑖𝑛𝜔𝑡𝑑𝜔𝑡 𝜋 0 𝐷 𝜋 = ∫ 𝐼 𝑠𝑖𝑛𝜔𝑡𝑑𝜔𝑡 = 2𝜋 0 𝑜𝑢𝑡 𝐼𝑜𝑢𝑡 (2.22) 2 𝐼𝑜𝑢𝑡 𝜋 . (2.22) Therefore, the efficiency can be calculated by 𝜂= 𝑃𝑜𝑢𝑡,𝑓𝑢𝑛𝑑 𝑃𝐷𝐶 = 𝑉𝑜𝑢𝑡 𝐼𝑜𝑢𝑡,𝑓𝑢𝑛𝑑 𝑉𝐷𝐶 𝐼𝐷𝐶 = 1 4𝑉𝐷𝐷 𝐼𝑜𝑢𝑡 2 𝜋 2 𝐼 𝑉𝐷𝐷 𝑜𝑢𝑡 𝜋 = 100% . (2.23) The voltage across the switch approaches a rectangular waveform as the third harmonic becomes stronger. Interestingly, if the drain current is assumed to be a half sinusoid, then it contains no third harmonic. However, in reality, the waveform exhibits some third-order distortion because the transistor I/V characteristic notably deviates from a square law. On-chip capacitor and inductor tank can be used to tune at the third harmonic to approximate the quarter wave transmission line shown in Figure 2.9. Moreover, this type of PA is very difficult to implement in practice, because the output network is more complex than in the case of either the class-D or –E PA. Output capacitance of device is not naturally absorbed into network, so it needs inductor to tune it out. Also, it is difficult to control more than fifth harmonic; the resonators are lossy and additional losses present diminishing returns on efficiency. Therefore, class-F PA is not widely used in RF CMOS design application. 2.5 Inverse Class-F Power Amplifier Inverse class-F PA [60], [61], shown in Figure 2.10, gives more efficiency than the traditional class-F PA. The main difference of the inverse class-F PA from the traditional 21 class-F PA is the output harmonic tuning method. In inverse class-F PA, the even harmonics is tuning instead odd to shape the drain current to be a square waveform, and the drain to source voltage will be a half-sinusoidal waveform as shown in Figure 2.11. This type of PA contains the output tuning circuit with even harmonic and fundamental harmonics frequencies. Therefore, the efficiency and the output power will raise due to nonoverlap between drain current and voltage because by tuning it we can achieve the square waveform drain current and half-sinusoidal waveform drain voltage. For some designs, this type of PA may reduce the voltage stress on the switching device because of the lower peak drain voltage. 2.6 Inverse Class-D Power Amplifier Inverse class-D [62-65] PA is the so called current-mode class-D PA, which is similar to the traditional class-D PA, but with interchanged voltage and current waveforms at the drain. The inverse class-D PA is often implemented differentially; half-side of the inverse class-D PA is shown in Figure 2.12. The waveforms are switched in as much as the current is a square and the voltage a half-sinusoid, shown in Figure 2.13. The main drawback of traditional class-D PA is that the drain capacitance of the transistors are not part of the matching network and need to be charged and discharged every cycle, leading to 𝐶𝑉 2 𝑓 power dissipation. While the inverse class-D PA can avoid this because 𝑉 = 0 when transistor switches from open to short. The inverse class-D PA has performance benefits in terms of either maximum frequency of operation, maximum power output, or transistor utilization. For a given transistor, the inverse class-D PA produces more power than any other design. Furthermore, there is no fundamental limit on the value of the shunt capacitance in inverse class-D PA, as it is included in the tank circuit. 22 A trade-off may be considered, however, for every large devices between the 𝑄 of the tank and the output power. Because there is no restriction on source capacitance, the maximum usable frequency of the inverse class-D PA is much higher than for class-E, given the same transistor. 2.7 Class-G Power Amplifier The last type of switching power amplifier to be looked at is the class-G PA [19], [66], shown in Figure 2.14, which uses multiple power supply voltages. Most PAs exhibit lower efficiency as the output power is decreased because their static DC power remains constant. The main idea to design class-G PA is to use multiple voltages to create multiple peaks in the overall efficiency characteristic. Because of the output resistance proportional to the square of the supply voltage, leading to a reduction in supply voltage by a factor of two reducing the optimum termination impedance by a factor of four, the low voltage is the key reason for poor efficiency in CMOS PA. The cascode topology in class-G PA act as switches between the twice supply voltage and ground. Efficiency in power back-off can be improved by reducing the supply voltage for envelope signals that are small enough [18], [19], [67]. The second switching path is added with a supply voltage of 𝑉𝐷𝐷 . It is critical to match the resistances of both the pull-up and the pull-down paths. Therefore, the class-G PA can increase the peak output power and improve the efficiency at power back-off simultaneously. 23 2.8 Summary The PAs continue to be dominant energy consumers in the most wireless transceivers. The mentioned above PAs cover the most of the recent PA design and provide a good working basis. Linear PAs in CMOS are inefficient when delivering high ouput powers, owing to low gain and losses in the output matching networks. Furthermore, they are also not linear due to parasitic effects, meaning that they must be operated at significant output power backoff to meet fidelity specifications. Though the switching PAs can achieve very high efficiency compared with that of linear PAs and take advantage of the benefits of CMOS scaling, there is little or no sensitivity to amplitude fluctuations at input. Therefore, they must be linearized with external circuitry. In the next chapter, several linearization techniques are proposed. 24 Figure 2.1. Generic configuration for linear PAs. Note the bias condition distinguishes between class-A, -B, -AB, and -C. 25 Figure 2.2. Drain voltage and drain current for ideal class A, AB, B, and C. 26 Figure 2.3. Schematic of typical class-D PA. 27 Figure 2.4. Class-D PA drain waveform. 28 Figure 2.5. Schematic of typical class-E PA. Figure 2.6. Class-E PA drain waveform. 29 Figure 2.7. Schematic of typical class-F PA. Figure 2.8. Class-F PA drain waveform. 30 Figure 2.9. Schematic of typical class-F PA with on-chip terminations. Figure 2.10. Schematic of typical inverse class-F PA. 31 Figure 2.11. Inverse class-F PA drain waveform. Figure 2.12. Schematic of typical inverse class-D PA. 32 Figure 2.13. Inverse class-D PA drain waveform. Figure 2.14. Schematic of typical inverse class-G PA. 33 Table 2.1. Conduction angles and duty cycles of linear PAs. Linear PAs Conduction Angle Duty Cycle Class-A 2π 100 % Class-AB π <2Φ<2π 50 %<D<100 % Class-B π 50 % Class-C 0 <2Φ<π 0<D<50 % Table 2.2. Ideal peak efficiencies of linear PAs. Linear PAs DC Power Output Power Peak Efficiency Class-A 2 𝑉𝐷𝐷 𝑅𝑜𝑝𝑡 2 𝑉𝐷𝐷 2𝑅𝑜𝑝𝑡 50 % 2 𝑉𝐷𝐷 2𝑅𝑜𝑝𝑡 50 %< η <78.5 % 2 𝑉𝐷𝐷 2𝑅𝑜𝑝𝑡 78.5 % (π/4) 2 𝑉𝐷𝐷 2𝑅𝑜𝑝𝑡 78.5 %< η <100 % Class-AB 2 𝑉𝐷𝐷 𝑅𝑜𝑝𝑡 𝑜𝑝𝑡 2 𝑉𝐷𝐷 𝜋𝑅𝑜𝑝𝑡 Class-B Class-C 𝑉2 < PDC <𝜋𝑅𝐷𝐷 2 𝑉𝐷𝐷 𝜋𝑅𝑜𝑝𝑡 2 𝑉𝐷𝐷 < PDC <2𝑅 𝑜𝑝𝑡 CHAPTER 3 LINEARIZATION TECHNIQUES Modern high-speed wireless communications demand transmitter architectures that are simultaneously highly efficient and linear when amplifying signals with high peak-to-average power ratio (PAPR) signals and large output powers, meaning that the amplifier operates at a significantly reduced amplitude from its peak at the majority of the time. A linear PA is most efficient when operating near its peak output power, because most of the quiescent current is used to amplify the signal; hence, amplifying signals with large PAPR is very inefficient. The switching PA ideally operates with no power dissipation due to nonoverlapping voltage and current signals at the transistor drain as discussed in the previous chapter. However, the linearization circuitry for normal operation on wideband linear communication signals (e.g., LTE, and Wi-Fi) [39], [68], [69] is required. Techniques such as envelope elimination and restoration (EER) [20], [22], [70], outphasing/LNIC/Chireix [1], [24], [71], pulse-width and pulse-position modulation [27], [26], digital polar PAs [19], [37], [38], and digital-Doherty [72-74] have been used. However, in each case they rely on polar components of the nonconstant envelope modulated signal, which require high bandwidth amplitude and/or phase modulators that are difficult to produce in CMOS and require significant static power consumption. An 35 alternative to techniques that require a polar conversion is to digitally modulate and sum the 𝐼 and 𝑄 signals in the Cartesian domain. In recent years, quadrature digital PAs [3133] have been proposed. They can reduce the challenges associated with polar conversion and modulation. In this chapter, the linearization systems will be discussed in detail, such as EER, outphasing/LINC/Chriex, pulse-width and pulse-position modulation, digital polar PAs, and quadrature PAs. The advantages and disadvantages will also be analyzed. 3.1 Envelope Elimination and Restoration The basic idea for EER technique is that any band-pass signal can be represented as an amplitude 𝐴 and phase 𝜙. This observation leads to the idea of decomposing the signal into an envelope signal and a phase-modulated signal, amplifying each separately, and combining the results at the end. Figure 3.1 shows the block diagram of the envelop elimination and restoration with a high efficiency switching PA. In-phase (𝐼) and quadrature phase (𝑄), signals can be transformed into the amplitude 𝐴 and phase 𝜙 signals using a complex coordinate rotation digital computer (CORDIC). The resulting phase information is processed by a highly-efficiency switching PA whereas the amplitude signal is applied as the output from a power supply modulator as the power supply voltage of the PA. The principle advantage of EER over feedforward and feedback techniques is that it requires no linearity in the PA core, allowing the output stage to be designed for maximum efficiency. However, a significant drawback of EER is that the transformations from Cartesian to polar coordinates are nonlinear [75], [76]. The Cartesian to polar 36 transformation can be given as follows: 𝐴(𝑡) = √𝐼(𝑡)2 + 𝑄(𝑡)2 𝜙(𝑡) = 𝑡𝑎𝑛−1 𝑄(𝑡) 𝐼(𝑡) . (3.1) (3.2) The nonlinear conversion from Cartesian to polar results in a significant bandwidth expansion, which limits wideband operation required by modern wireless communication standards. The bandwidth for the amplitude component is about two to three times than the bandwidth of the Cartesian components, while the phase component is about ten times than bandwidth of the Cartesian components [39]. Because these signals will be processed by systems with finite bandwidth before recombination, degradation in EVM and spectral regrowth is possible. Furthermore, the delay mismatch between the total phase shift and gain of the two paths must be maintained below an acceptable level. The first reason for delay mismatch is that the amplitude and phase information is up-converted to RF experiences a greater group delay as it traverses interconnects. The second reason is that the amplitude and phase information paths are both bandwidth limited; a power supply modulator limits the former and a phased-locked loop the latter. Additionally, the phase modulators incorporating active stages such as differential pairs exhibit substantial AM to PM conversion at high frequencies, corrupting the phase path. Moreover, using the CORDIC has some issues. First, it can realize by using a complex algorithm; second, the CORDIC circuit is nonlinear; third, the system complexity makes it difficult to meet the stringent linearity. Based on the issues mentioned above, integration of EER PA systems is problematic, which limits its viability. 37 3.2 Outphasing/LINC An interesting approach called outphasing architecture to avoid amplitude variations in a PA system was first introduced by Chireix in 1935 [24]. It is also called linear amplification with nonlinear components (LINC) [77], [78]. As shown in Figure 3.2, the input signal is converted into two phase-modulated pulse waves with constant amplitude by outphasing generator. The two generated pulse waves can drive two identical switching PAs and their output sum together using a passive power combiner. If 𝑆1 (𝑡) and 𝑆2 (𝑡) are generated from the input signal 𝑉𝑖𝑛 (𝑡), amplified by means of nonlinear stages, and subsequently added, the output contains the same envelop and phase information as in 𝑉𝑖𝑛 (𝑡). The output power can reach maximum when the two pulse waves are in-phase, while the output power is zero when the two pulse waves are 180 degree out-of-phase. In this case, we assume that the two switching PAs are identical. The phases of the input signal can be given as follows and shown in Figure 2.3: 𝑆1 (𝑡) = 𝐴0 cos(𝜔𝑡 + 𝜙(𝑡) + 𝜃(𝑡)) (3.3) 𝑆2 (𝑡) = 𝐴0 cos(𝜔𝑡 + 𝜙(𝑡) − 𝜃(𝑡)) (3.4) 𝑆(𝑡) = 𝐴(𝑡) cos(𝜔𝑡 + 𝜙(𝑡)) (3.5) where 𝜔 is the carrier frequency, and 𝜃(𝑡) is expressed by 𝜃(𝑡) = 𝑎𝑟𝑐𝑐𝑜𝑠 𝐴(𝑡) 𝐴0 . (3.6) Realization of 𝑆1 (𝑡) and 𝑆2 (𝑡) from the input signal requires substantial complexity, primarily because their phase must be modulated by 𝜃(𝑡), which itself is a nonlinear function of 𝐴(𝑡), as shown in (3.6). The use of nonlinear frequency-translating feedback loops has been proposed [79], [80], but loop stability issues limit the applicability of these techniques. 38 In addition to complexity, outphasing/LINC must deal with two other important issues. First, gain and phase mismatch between the two signals paths results in residual distortion [81]. Second, the output combiner introduces significant loss because it must achieve a high isolation between the two PAs. As for the two switching PAs, in order to cancel out each other for the out-of-phase situation, the two switching PAs must be precisely matched. This limits the minimum output power of the outphasing PA, therefore degrading the dynamic range of the system. Furthermore, the efficiency of the outphasing PA is angle dependent since the two switching PAs operate at their full power. The efficiency is lowest when the two paths are 180 degree out-of-phase. 3.3 Pulse-Width and Pulse-Position Modulation Pulse-width modulation (PWM) is a modulating scheme in which the duration or width or time of the pulse carrier varies proportional to the instantaneous amplitude of the message signal. Consequently, the information is coded into the pulse time position within each switching interval. PWM only requires synthesis of a few discrete output levels, which is easily realized by topologically simple high efficiency switching power stages. Pulse-position modulation (PPM) is a modulating scheme in which the amplitude and width of the pulsed remains constant, while the position of each pulse, with reference to the position of a reference pulse varies according to the instantaneous sampled value of the message signal. Each pulse has identical shape independent of the modulation depth. This is an attractive feature, since a uniform pulse is simple to reproduce with a simple switching power stage. In switching PA, the input pulse-width can be directly related to the output power. 39 Therefore, the output amplitude can be modulated by pulse-width modulation. While, the phase change can be modulated by pulse-position modulation. This leads to the pulsewidth and pulse-position modulation (PWPM) shown in Figure 3.2 and Figure 3.3 [26], [79], [82]. A Fourier expansion of a PWPM signal reveals that the relationship between the fundamental envelope amplitude 𝐴1 (𝑡) and the duty cycle 𝐷(𝑡) [26] 𝐴1 (𝑡) = 4 𝜋 sin(𝐷𝜋). (3.7) As the duty cycle is varied, harmonic tones are expressed [26]: 𝐴1 (𝑡) = 4 𝑛𝜋 sin(𝑛𝐷𝜋) (3.8) where n is the harmonic number. As seen from the equation, similar to phase modulation in both EER and ouphasing/LINC PAs, the phase modulation is contained in the position of the edges of the phase-modulated pulse wave. PWPM modulation, shown in Figure 3.4, works well for system that use modulation standards with moderate PARs (~ 3-6 dB). Same as EER PA, the bandwidth expansion is also present in the amplitude and phase waveform generation. Furthermore, the output dynamic range of the PWPM modulation PA is limited by the minimum width of the input pulse wave that the transistor switches can process without pulse swallowing. 3.4 Digital Polar PA Digital polar modulation [35], [36], [37], [38] is another technique to linearize the switching PA. This technique provides a digital friendly means of amplifying nonconstant envelop modulation that interfaces directly with digital signal processing. They can generally be broken down into individual switching PA, as shown in Figure 3.5. Instead 40 of using one switching PA to amplify the RF signal, a number of unary weighted switching PA is applied to provide amplitude modulation. By adjusting the number of the active switching PAs, the amplitude can be modulated at the output. The drawback of this technique is the same as the EER PA. The amplitude and phase propagate at different frequencies, so there are different group delays, resulting in the delay mismatch. In addition, the conversion from 𝐼 and 𝑄 to amplitude and phase is nonlinear; therefore, the bandwidth expansion will limit the wideband operation of the PA. Moreover, the finite AM resolution is limited by the number of PA cells, and this AM quantization error generates a white noise in the spectrum [36]. 3.5 Quadrature Switching PA Unlike the linearization technique mentioned above, the quadrature [31-33] switching PA digitally modulate and sum the 𝐼 and 𝑄 signals in the Cartesian domain, as shown in Figure 3.6. In the capacitively combined version, the capacitor array is divided into 𝐼 and 𝑄 subarrays, each with a quantized number of unary/binary capacitor cells. The 𝐼/𝑄 vectors can be represented simply by clocking the 𝑄 cells with a quadrature clock delayed by 90 degrees from the 𝐼 clock; 𝐼/𝑄 vectors can be weighted by controlling the number of cells that are switched in each subarray. A four quadrant operation in the complex plane is achievable by appropriately inverting the 𝐼 and 𝑄 clock signals. The output amplitude and phase are achieved by appropriate weighting of the 𝐼/𝑄 signals, which eliminates the need for a CORDIC, and a wideband supply modulator and phase modulator required for realization of above mentioned EER/polar PAs. Furthermore, 𝐼/𝑄 vectors propagate at similar frequency with similar group delay, the delay mismatch can 41 be avoided. The drawback of this technique is the power loss compared with conventional digital polar PA. The power ratio comparing a quadrature system with a polar system can be calculated as follows: 𝑃𝑙𝑜𝑠𝑠 = 10𝑙𝑜𝑔10 𝜋 4 2 𝑉𝐼.𝑄 𝑐𝑜𝑠2 ( ) 2 𝑉𝐼.𝑄 = −3 dB (3.9) where 𝑉𝐼,𝑄 represents the maximum amplitude of summation of the two vectors when the amplitudes of 𝐼 and 𝑄 are equal. Therefore, the ouput power of a quadrature system is reduced by 3 dB when compared with the vector summation of two signals that are in phase. In similar, the average output power ratio is calculated as follows: 1 2𝜋 ̅̅̅̅̅̅ 𝑃𝑙𝑜𝑠𝑠 = 2𝜋 ∫0 1 (|𝑐𝑜𝑠𝜙|+|𝑠𝑖𝑛𝜙| 2 dϕ = 𝜋 ≈ −1.96 dB . (3.10) Therefore, the output power of a quadrature system is 2 dB lower on average than that of the digital polar SCPA. The loss of output power can be alleviated by increasing the number of basis phases to be greater than 4. Therefore, the multiphase [41] systems is proposed recently, which will be discussed in Chapter 5. 3.6 Summary The first four linearization techniques presented converting the 𝐼 and 𝑄 information to amplitude and phase information from Cartesian coordinate to polar coordinate. The first deficiency is the bandwidth expansion that limits the capability to operate in closed loops. The second drawback is that those techniques suffer from delay mismatch due to the group delay differences that the amplitude and phase signals experience. While the quadrature systems avoid the bandwidth expansion and delay 42 mismatch, as well as the elimination of the supply modulator or/and phase modulator because the expanded bandwidth of the quadrature generation does not need to be modulated in a closed loop and does not propagate at different frequencies than the envelope. The only drawback is the output power lower than that of the conventional polar PA. The multiphase architecture can overcome all of the drawbacks mentioned above, which will be discussed in Chapter 5. The PA is the core of in the transmitter beamforming chain. The next chapter will discuss about the different architecture of phased arrays. 43 Figure 3.1. Block diagram of an EER PA. Figure 3.2. Block diagram of an outphasing/LINC PA. 44 Figure 3.3. Outphasing operation in polar coordinates. Figure 3.4. Block diagram of a PWPM PA. 45 Figure 3.5. Block diagram of a digital polar PA. Figure 3.6. Block diagram of a quadrature PA. CHAPTER 4 PHASED ARRAY ARCHITECTURES A phased array creates a beam of radio waves that can be electronically steered to point in different directions, without moving the antennas. In the phased array, the radio frequency current from the transmitter is fed to the individual antennas with the correct phase relationship, so that the radio waves from the separate antennas add together spatially to increase the radiation in a desired direction, while cancelling to suppress radiation in undesired directions. Figure 4.1 shows the concept of phased array antenna that uses phase shifters to electronically steer the beam over the scan sector. The RF source produces a waveform that is divided up into individual paths called element channels, each containing a phase shifter and power amplifier. Beams are formed by shifting the phase of the signal emitted from each radiating element, to provide constructive/destructive interference so as to steer the beams in the desired direction. Figure 4.2 shows an idealized element radiation pattern that covers the scan sector, which signal strength dropping outside of the sector. When all the phase shifters of the array are properly aligned, the array produces a main beam in the desired pointing direction. For an N element phased array, as N increases, the beam becomes more focused, with a corresponding increase in channel capacity, therefore improving the effective signal to noise ratio. 47 Phased arrays primarily are widely used for radar applications [83], [84]. Most of these applications are for military purposes and less concerned with cost so that they are usually implemented using discrete components or high performance semiconductors such as GaAs or SiGe. One example is the development of short-range vehicular radar systems for collision prevention and driver assistance [85]. Another communication application is the prevalence of low cost MMIC phased array implementations coupled with the growing demand for high data rate wireless communications. In recent years, there has also been interest in the use of phased arrays for broadband wireless access systems, which use wireless links to bridge the last mile between the subscriber and the service provider [86]. Other promising research has been focused on combining beamforming with other MIMO techniques to maximize spectral efficiency [87]. This idea is incorporated to be released IEEE 802.11n standard for wireless LANs, which uses MIMO spatial multiplexing techniques with optional beamforming. The move of phased array into the consumer electronics domain necessitates low cost and compact systems, which points to fully integrated CMOS implementations. This chapter mainly discusses the different architectures for phased array. The architectures can be grouped into two categories: analog implementation and digital implementations, which will be discussed in detail. 4.1 Analog Phased Array There are a number of different analog phased array architectures, depending on the position of the phase shifters in the transmit chain. Based on the stage in which phase 48 shifting is performed, analog phased arrays can be categorized into three district types: RF phase shifting, LO phase shifting, and IF phase shifting. Each of these types of analog phased arrays will be discussed as follows. Figure 4.3 shows the general architecture of phased array using RF phase shifting, which has been the dominant architecture of phased arrays ever since they were developed [88]. In this architecture, the signals at the antenna elements are phase shifted and combined in the RF domain. One advantage of designing phased arrays using RF phase shifting are its simplicity, system-level linearity, and low power consumption. Since this technique only requires a single mixer and there is no need of LO signal distribution, only the antennas and phase shifters must be duplicated. Therefore, it usually results in the most compact architecture among other phased array designs [89-92]. Another advantage is that the signal after the RF combiner has a high pattern directivity and can substantially reject an interferer, thus greatly relaxing the linearity requirement of the transceiver electronics. Therefore, the requirement on dynamic range of down conversion mixer is not as stringent as other types of phased array architectures. The main challenge of using phase shifting in RF path in the design of phased arrays is implementing high performance phase shifters capable of operating at RF frequencies. In general, they tend to be excessively lossy at microwave and millimeter regime [93], [94] while active phase shifters usually suffer from low dynamic range [95], [96]. Dynamic range of phased shifters is particularly important in the operation of phased arrays as phase shifters are required to operate in the presence of strong interferers. Another factor that should be taken into consideration is the amplitude variation of the signal at each channel. 49 As the signal combining and null forming at undesired directions is significantly affected by the amplitude of the signal at each channel, the phase shifters are required to not just have a low insertion loss but also maintain a constant loss within their phase tuning range. The second choice is to apply the phase shifter to the LO signal before it is applied to the mixer shown in Figure 4.4. The phase of RF signal at each channel is basically the sum of phases of IF and LO signals. Therefore, tuning the phase of LO signals would translate into changing the phase of RF signals. The advantage of designing phased array using LO phase shifting compared with other architecture is that the phase shifters are not placed on the signal path [97], [98]. In this case, the nonlinearity, the loss, and the noise performance of the phase shifters would not have a direct impact on the overall system performance. Another advantage is that the performance of the required phase shifter on LO signal path, such as bandwidth, linearity, and noise figure will not be as stringent as the phase shifters on the signal path [99]. Another attractive thing is that it relaxes the requirement for the phase shifter to have constant amplitude for varying phase shifts. Since the mixers are typically hard driven, the LO stages are operated in saturation, and variation in the phase shifter output will have a reduced impact. LO phase shifting architecture also requires the use of an LO distribution network, which can be complicated for large arrays so that the power and area consumption is large. Also, in satellite or defense based application, the required LO phase noise is very low, and this can only be achieved using an external oscillator, such as a dielectric resonator oscillator, and it removes the advantage of integrated silicon based oscillators [100]. The last analog phased array architecture is IF phase shifting shown in Figure 4.5, 50 which is desirable from the standpoint that it is easier to realize accurate phase shifts at lower frequencies. As mentioned before, the phase of RF signal at each channel is the sum of phases of IF and LO signals. Therefore, tuning the phase of RF signals can be achieved by tuning through tuning the phase of IF signal [101], [102]. The advantage of the IF phase shifting architecture is that the phase shift is done in the IF path, resulting in a straightforward IF power combining network, which is easy for narrowband systems. Additionally, phase shifting is performed at much lower frequencies; therefore, designing phase shifter with much better performance can be possible at IF path. As a result, the nonlinearity, the loss, and the noise performance of the phase shifters can be much better when IF phase shifting is used. However, a mixer is required at each antenna element, which is subjected to interference from all directions because of the wide antenna element pattern, thus generating intermodulation products that propagate throughout the array. Another disadvantage is that there will be increased power and area consumption, and the phase shifters themselves will be larger since the passive components required in a phase scale are in inverse proportion to the frequency of operation, so inductors and capacitors will be larger than they would be if the phase shifter was operating at RF. Furthermore, since the interfere cancellation occurs only after the IF stage, all the mixers are required to have a high level of linearity capable of handling strong interference emanating from undesired directions. 51 4.2 Digital Phased Array An alternative approach in the design of a phased array is to use digital beamforming that consists of the spatial filtering of a signal where the amplitude scaling, phase shifting, and adding are implemented digitally. The typical block diagram of digital beamforming phased array is shown in Figure 4.6. Control messages are for setting time. The digital data from the modules are combined in a digital beamforming and processing system, and module synchronization is accomplished by supplying each module with a common clock signal. Phased array based on digital beamforming techniques have also been developed [103-105]. In this architecture, each antenna element is connected to an 𝐼/𝑄 transmitter, and the transmitted 𝐼/𝑄 signals are digitized and sent to a baseband digital beamforming network. The main advantage of the digital array is its multifunction capability such as creating many beams [106]. An extensive variety of complex, signal processing algorithms can be implemented using DSP units. For instance, multibeam and multiple-input-multipleoutput (MIMO) functionality can be achieved by the digital phased arrays. Such phased arrays can be capable of distinguishing among desired signals, multipath and interfering signals, as well as demonstrating their directions of arrival. Moreover, digital phased arrays can adaptively update their beam patterns, so as to track the desired signal with the main lobe of the beam and track the interferers by placing nulls in their directions. 4.3 Summary Two categories of the phased arrays are discussed in details. In analog beamforming, amplitude/phase variation is applied to analog signal. The advantage of the 52 analog techniques is that they provide drastic reductions in power dissipation and fabrication costs, since they eliminate the need to duplicate the entire RF chains between the different branches [107]. Their limitation is that since the phase shifter introduced after the baseband signals have been combined, they are limited to single user or point to point communications. In digital beamforming, the advantage of this approach lies in its flexibility, and its capacity for multiuser beamforming. It allows multiple beams to be formed and directed to an arbitrary number of users. The proposed digital beamforming transmitter will be presented in Chapter 6. In next chapter, a C-2C split-array multiphase SCPA will be proposed, which is the core part of the proposed digital beamforming transmitter. 53 Figure 4.1. Basic concept of phased array. Figure 4.2. Idealized element radiation pattern. 54 Figure 4.3. Phase shifting in RF path. Figure 4.4. Phase shifting in LO path. Figure 4.5. Phase shifting in IF path. 55 Figure 4.6. Block diagram of digital phased array. CHAPTER 5 SPLIT-ARRAY, C-2C SWITCHED-CAPACITOR POWER AMPLIFIERS 5.1 Introduction The pursuit of high data rates in wireless communications has led to the prevalence of nonconstant envelop (nonCE) modulation with high peak-to-average power ratios (PAPR, e.g., Wi-Fi and long-term evolution for 3G (LTE)). Because efficiency is inversely proportional to output power, linear power amplifiers (PAs) are inefficient when outputting less than peak output power, as is the average for large PAPR signals. Switching PAs are more efficient when compared to linear counterparts; additionally, CMOS scaling focuses on optimization of transistors as low-loss and high-speed switches [108], rather than as linear transconductors [109]. However, due to their limited sensitivity to input signal amplitude, external linearization techniques are required. Techniques such as envelope elimination and restoration (EER) [20-22], outphasing/Chireix [23-25], pulse-modulation [26], [27], and digital-Doherty [28-30] have been proposed, but in each case they rely on polar components of the nonCE modulated signal. The polar components require high bandwidth amplitude and/or phase modulators that are difficult to build in CMOS. Additionally, these circuits can require significant static power consumption and/or more chip area. Furthermore, the bandwidth expansion involved with polar conversion [39], [69] limits the capability to operate in closed loops, 57 and the systematic errors (e.g., group delay, finite bandwidth, etc.) dominate the overall nonlinearity. Conventional switched-capacitor PAs (SCPAs) operate as polar transmitters (TX), combining the functions of a DAC, baseband filtering, frequency up-conversion, and amplification into a single block. They are versatile and can be readily tuned to different frequencies and power levels and scaled with process changes [19], [38]. They suffer from the drawbacks of all polar TXs, with the additional drawback of being quantized. Quantization noise from prior SCPAs dominated the out-of-band (OOB) noise, which is typically only filtered by a resonant matching network at the output. In recent years, quadrature [31-33] and multiphase [41] digital PAs have been proposed. Quadrature- and multiphase- SCPAs (Q-SCPA and MP-SCPA, respectively) reduce the challenges associated with polar conversion and modulation [33], while leveraging the other benefits of the SCPA. They do not suffer the same systematic nonlinearity as polar TXs, but they do suffer from reduction in output amplitude when compared to polar systems [42]. The Q-SCPA is a special case of the MP-SCPA, where the number of phases, M, is equal to 4. Q-SCPAs have a phase-dependent power drop caused by the 90-degree phase difference of the I and Q signals. Additional basis phases can be used to decrease the phase difference (e.g., increase constructive summation). Still, the critical challenge for prior SCPA designs is their output resolution limiting the OOB noise. The minimum available size of a capacitor in each CMOS process and the associated matching due to the process, voltage and temperature (PVT) variations determine the maximum resolution of prior SCPAs. Split-array SCPAs (SA-SCPA) [43], [44] are introduced to overcome the 58 challenges of simultaneously designing SCPAs with high resolution and high output power. Split-arrays, shown in Figure 5.1a, allow a capacitance array to be subdivided with the aid of an attenuation capacitor, CA, to balance the charge between the arrays, regardless of the size of the arrays, or their associated capacitance. This allows a reduction in the area and allows for array capacitance to be scaled to usable values for high resolution arrays. The LSB subarray capacitance, in series with the capacitance from C A presents, the equivalent of a unit capacitance in the MSB subarray. More than one split can be added to an array, but linearity is sensitive to matching and parasitic effects from CA. C-2C arrays [33] are widely used because of the low ratio of the maximum-to-minimum capacitance, which allows for better capacitor matching [45], at the expense of sensitivity to parasitic effects [46], [47]. The size of the C-2C array increases linearly with the resolution, thus occupying less area then a binary-weighted array. The sizes of the capacitors are fixed and small, making the switches see approximately the same small capacitive load, thus easing the switch design as well as the layout, since the entire topology is composed of the replicas of a small C-2C block. 5.2 Theory of Operation 5.2.1 Conventional SCPA Taking advantage of low-loss, fast CMOS switches, area-efficient capacitors and precisely-controlled capacitance ratios, the SCPA is becoming commonly used for RFmixed-signal circuit design [19], [38]. The SCPA is an arrayed class-D PA that controls the output voltage using a capacitive voltage divider at its output. The core of the SCPA is a logic-gated inverter driving one plate of a capacitor, and whose opposite plate is common 59 to an array of such circuits. The gating logic controls whether the capacitor is switched at the RF carrier frequency or held at a fixed-potential. The common top-plates are connected to an inductive impedance and load resistance, typically, via an impedance matching circuit. The matching circuit is tuned such that an equivalent RLC circuit is realized and tuned to select the RF carrier frequency, while rejecting harmonics of the switching waveform. Several unit capacitors share a common plate, while the other plates are selectively driven by phased-modulated pulse-waves, switching between the supply voltage (𝑉𝐷𝐷 ) and ground (𝑉𝐺𝑁𝐷 ) or held at 𝑉𝐺𝑁𝐷 . By controlling the ratio of the total capacitance switched between 𝑉𝐷𝐷 and 𝑉𝐺𝑁𝐷 , arbitrary voltages can be generated at the output. If switching all N capacitors, peak voltage is generated, while switching only some of the capacitors reduces the output voltage proportional to the n total capacitors that are switched. The output voltage, Vout, is then given by the following: 𝑉𝑜𝑢𝑡 = 2 𝑛 𝜋 𝑁 𝑉𝐷𝐷 (5.1) where 2/π is the Fourier coefficient for the fundamental frequency of the square switching wave. The output power is given by the square of the RMS value of the output voltage, divided by the load resistance it is driving, Ropt: 𝑃𝑜𝑢𝑡 = 2 𝜋2 2 𝑛 2 𝑣𝐷𝐷 (𝑁) 𝑅𝑜𝑢𝑡 . (5.2) An SCPA design begins by choosing Ropt to provide the desired output power. The input power is due the power dissipated in charging the total input capacitance to its final voltage: 2 𝑃𝑖𝑛 = 𝐶𝑖𝑛 𝑣𝐷𝐷 𝑓0 (5.3) where 𝐶𝑖𝑛 is the input capacitance that varies with the selected input code, n, and 𝑓0 is the 60 operation frequency. Cin is given as 𝐶𝑖𝑛 = 𝑛(𝑁−𝑛) 𝑁2 𝐶 (5.4) C is the total capacitance in the array. The efficiency of the SPCA is determined by the ratio of output power to total power: 𝜂𝑆𝐶𝑃𝐴,𝑖𝑑𝑒𝑎𝑙 = 𝑃𝑜𝑢𝑡 𝑃𝑖𝑛 +𝑃𝑜𝑢𝑡 = 4𝑛2 4𝑛2 + 𝜋𝑛(𝑁−𝑛) 𝑄𝑁𝑊 (5.5) where 𝑄𝑁𝑊 represents the loaded quality factor of the equivalent RLC network, which is given by the following: 𝑄𝑁𝑊 = 𝑋 𝑅𝑜𝑢𝑡 = 1 2𝜋𝑓0 𝐶𝑡𝑜𝑡 𝑅𝑜𝑢𝑡 (5.6) 𝐶𝑡𝑜𝑡 is the total capacitance in the array (i.e., the sum of all unit capacitances). In practice, the choice of 𝑄𝑁𝑊 is dominated by the quality factors of integrated CMOS inductors. Typically, the qualify factor of on-chip inductors is < 20. The efficiency for a two-element downward transforming impedance match, comprising an inductor and capacitor, can be given by [110] 𝑄 1− 𝑁𝑊 𝜂𝑚𝑎𝑡𝑐ℎ = 𝑄𝑐𝑎𝑝 𝑄𝑁𝑊 1+ 𝑄𝑖𝑛𝑑 ≈ 1 𝑄 1+ 𝑁𝑊 𝑄𝑖𝑛𝑑 (5.7) The total drain efficiency, 𝜂𝑡𝑜𝑡 , of the SCPA is the product of (5.4) and (5.6): 𝜂𝑡𝑜𝑡 = 𝜂𝑆𝐶𝑃𝐴,𝑖𝑑𝑒𝑎𝑙 𝜂𝑚𝑎𝑡𝑐ℎ (5.8) 𝜂𝑡𝑜𝑡 is plotted versus QNW (Qind=15) in Figure 5.2, and it shows a convex optimum. The optimum QNW is between 2-4 for typical inductor quality factors in integrated RF CMOS processes. It is noted that inductors with high Qind would allow a proportionally higher network quality factor to achieve optimal efficiency. 61 5.2.2 Operation of MP-SCPA Unlike the original SPCA that used polar multiplication to achieve a linear output, the MP-SCPA utilizes vector summation, where the SCPA weights and sums a set of basis vectors using a capacitor array. Conceptually, in an MP-SCPA, the capacitor array is divided into subarrays that are clocked by different phases of an MP clock. The arrays are typically “shared” [41]. A set of basis clock phases that span the unit circle are generated by an MP clock generator. The phases are typically uniformly spaced. Two of the phases clock the SCPA such that the capacitor array weights each basis vector. Charge redistribution on the common plate of the capacitors allows the vector summation of the two weighted phases so that the output has the desired amplitude and phase corresponding to the input amplitude and phase modulation. Typically, adjacent phases are summed, but the MP-SCPA is not inherently limited to summing adjacent clock phases. It can also sum more than two phases. The only requirement is that the charge contribution of each phase should settle before another phase is input. An example of a 16 phase MP-SCPA is shown in Figure 5.3. An MP clock generator, which can be created with a phased-locked loop (PLL), delay-locked loop (DLL), polyphase filter, or a multistage ring-oscillator, is used to generate RF clock signals that are divided into 16 output phases (ϕ1 to ϕ16). From the 16 phases, the two adjacent output phases (e.g., ϕ1 and ϕ16) that are closest to the desired PM phase are routed to an MP logic decoder. The logic decoder decides whether an individual capacitor in the array is switched on ϕ1, or ϕ16, or held at ground. In this way, the basis phases are weighted and summed. The number of basis phases can be different than 16, and it does not have to be 62 symmetric. If fewer phases are used, the maximum output power is reduced, while if more phases are used, more complex DSP and faster charge settling requirements are required. The normalized output power of an MP-SCPA as a function of the number of cells switched on phase 1, n1, phase 2, n2, the total number of cells, N, and the number of phases, M, is provided in below [41]: ||𝑃𝑜𝑢𝑡 || = 2𝜋 ) 𝑀 𝑛12 + 𝑛22 +2𝑛1 𝑛2 cos( 4𝑁 2 . (5.9) Figure 5.4 plots ‖𝑃𝑜𝑢𝑡 ‖ versus the number of switching capacitors (7-bit array) and the number of phase vectors, M. It is observed that there is a significant increase in output power when increasing the number of phases from M=4 to M=8 and again from M=8 to M=16, but not a significant jump when increasing M beyond 16. Another factor in choosing M is that the charge should settle on each capacitor that is switched on phase m before the beginning of phase m+1; with an increase in M, less time is available for settling between edges. Hence, interaction between the phases would cause nonlinearity. For further detail on the MP-SCPA, the reader is referred to [41]. 5.2.3 Operation of SA-SCPA A split-array allows for a capacitor array (Figure 5.1) to be divided into two, or more, subarrays with larger unit capacitors, mitigating the challenge of designing small MiM capacitors or using lossier, more parasitic laden vertical natural capacitors. In the split-array, an attenuation capacitor, CA, is placed in series between the LSB and MSB subarrays to allow for charge redistribution. The capacitor sizes on the LSB and MSB subarrays are given as follows: 𝐶𝐵0,𝐿𝑆𝐵 = 𝐶𝑡𝑜𝑡 2𝐿 (5.10) 63 𝐶𝐵𝐿,𝐿𝑆𝐵 = 𝐶𝐵0,𝐿𝑆𝐵 2𝐿 𝐶𝐵0,𝑀𝑆𝐵 = 𝐶𝑡𝑜𝑡 2𝑀+𝑙𝑜𝑔2 𝑁+1 𝐶𝐵𝑀,𝑀𝑆𝐵 = 𝐶𝐵0,𝑀𝑆𝐵 2𝑀 𝐶𝑈,𝑀𝑆𝐵 = 𝐶𝐵0,𝑀𝑆𝐵 (5.11) (5.12) (5.13) (5.14) where 𝐶𝑡𝑜𝑡 is the desired total size of capacitor array, L is the total number of binary weighted cells in the LSB sub-array, M is the total number of binary weighted cells in the MSB subarray, and N is the total number unary weighted cells in the MSB subarray. The attenuation capacitance is expressed as follows: 𝛴𝐶 𝐶𝐴 = 𝛴𝐶 𝐿𝑆𝐵 𝐶𝑈,𝑀𝑆𝐵 𝑀𝑆𝐵 (5.15) The capacitance seen from the input is given by (5.3). The maximum power occurs for n=N/2, corresponding to a half input code. Hence, the maximum input power based on equation (5.2) is found as 𝑃𝐼𝑁 = 1 𝐶 4 𝑡𝑜𝑡 2 𝑣𝐷𝐷 𝑓0 . (5.16) The minimum capacitor must be larger than the minimum geometry possible in each technology. Minimum sized capacitors offer poor matching; hence, using small capacitors reduces the SCPA linearity. Additionally, if binary weighted capacitors are used, the ratio of capacitance in the design grows geometrically, also reducing the matching accuracy: 𝐶𝑟𝑎𝑡𝑖𝑜 = 2𝑀 . (5.17) The resolution of the array is limited by the minimum capacitance available in the process for a given output power and network quality factor. Using a split array, allows larger capacitors to be used for the LSBs and hence enables increasing the resolution of the 64 SCPA, while being able to control Cratio. This comes at the expense of a slightly larger input power needed to switch larger capacitors in the LSB subarray(s). For best linearity and efficiency, an optimal design would minimize the product of the capacitance ratio and the input power. Hence, a figure of merit (FoM) is defined as follows [111]: 𝐹𝑂𝑀 = max(𝑃𝐼𝑁 )𝐶𝑟𝑎𝑡𝑖𝑜 (5.18) The position of CA can be located at any bit position between the LSB and the MSB, impacting the size of both arrays, which impacts both input power consumption and linearity. For all possible LSB subarray and MSB subarray combinations in Figure 5.1, the FOM versus position of the attenuation capacitance, 𝐶𝐴 , for a total capacitor array resolution of 16 bits is shown in Figure 5.5. The subarrays can be either binary weighted, unary weighted, or C-2C. It is noticed that due to higher FOM and worse performance compared with other configurations, the unary LSB, -binary MSB configuration is neglected. Only the switching losses and conduction losses of the output state are considered when calculating input power; all other kinds of power consumption would scale similarly for all of the varying designs. Owing to the same total capacitance and capacitance ratio for both binary LSB, binary MSB and binary LSB, unary MSB configurations, the binary-unary design is not pictured, though it is noted that the FoM of both are identical. In this case a binary-binary array will always be preferable to a binaryunary array due to its reduced size and no need for a decoder. An even split between the LSB and MSB subarrays (e.g., position of the attenuation capacitor is equal to half of the total number of bits) yields the best FoM for any array combinations except for C-2C-unary array. This is because the ratio of the maximum-to minimum capacitance is only two, which reduces the effect of mismatch and total 65 capacitance decreases when increasing the number of bits in the C-2C array. The total equivalent capacitance for a C-2C array increases linearly as the number of C-2C bits are increased. The unit capacitor in the C-2C segment should be equal to 1.5 times the unit capacitor in the unary array to achieve better resolution. C-2C segmented arrays uses the same number of unit cells as binary segmented arrays; hence, they preserve the area efficiency benefits. Moreover, they use the same unit cells throughout the C-2C array; hence, they provide better matching in the layout. However, nodal parasitics degrade their linearity. As seen from Figure 5.5, for C-2C arrays, the FOM is better when increasing the number of C-2C bits. However, the resolution of C2C arrays cannot be made arbitrarily high due to the nodal parasitics that will be discussed in the next section. Due to the trade-offs made to minimize the layout area, maximize the efficiency, and achieve good linearity simultaneously, a C-2C LSB, unary MSB configuration is chosen. Because the total capacitance seen by the switches of both C-2C and unaryweighted arrays are different, the size of the switches should be optimized in both subarrays to maximize the switching efficiency and minimize delay differences. The switches are sized using logical effort calculations to optimize the delay versus power consumption trade-off. Though the size of the unary-weighted unit capacitor is designed to be the same as that in the C-2C array to reduce the effect of mismatches in the capacitors, the resolution limit of C-2C arrays is still determined based on the mismatch due to PVT variations of the capacitors in the array [46], parasitics between internal nodes and the substrate [45], [47], [112] and the jitter limitation of the clock, which will be discussed in the next section. 66 5.3 Resolution Limit of C-2C Array In C-2C arrays the significant parameters affecting linearity are the capacitor matching and the intranodal parasitics, as well as the jitter. Jitter will not be examined here since the limit is well known and no different for any SC-DAC. Nodal parasitics, mismatch and their effects on integrated and differential nonlinearity (INL and DNL, respectively) will be examined in the following subsections. 5.3.1 Nodal Parasitic Unlike traditional unary or binary array capacitor arrays, the C-2C array has a major disadvantage due to the parasitic capacitances located at intermediate nodes inside the DAC, which are dependent on each bit rather than the segmentation number of the DAC. This is because some of the charge from the switching capacitors is distributed to the nodal parasitic capacitors during the conversion process, which effectively serves to change the voltage contribution from each capacitor in the array. These nodal parasitic effects of C2C arrays results in poor linearity at higher output resolutions; hence, they significantly limit the resolution of such arrays. The nodal parasitic capacitance associated with C-2C array is shown in Figure 5.6, where 𝐶𝑃 is the sum of bottom-plate and top-plate parasitic capacitances of the interconnecting capacitors (2C) and the top-plate parasitic capacitance of the branch capacitor (C). The output voltage of a parasitic laden C-2C array, for any codeword, n, can be expressed as follows: 𝑁 𝑉𝑜𝑢𝑡 = 𝛴𝑛=0 3𝐶 + 𝐶𝑅,𝑛+1 + 𝐶𝑃 𝐶 + 𝐶𝑅,𝑛+1 + 𝐶𝑃 • 𝑏𝑛 (𝑁−𝑛) 3𝐶 + 𝐶𝑅,𝑛+2 + 𝐶𝑃 𝐶 + 𝐶𝑅,𝑛+2 + 𝐶𝑃 ••• 3𝐶 + 𝐶𝑅,𝑁 + 𝐶𝑃 . (5.19) 𝐶 + 𝐶𝑅,𝑁 + 𝐶𝑃 CR,n+1 is the equivalent capacitance looking toward the output from any bit position, and bn 67 is the value of the codeword at bit position n. The equivalent capacitance is found as follows: 𝐶𝑅,𝑁 = 𝐶 𝐶𝑅,𝑁−1 = [𝐶𝑅,𝑁 + (𝐶 + 𝐶𝑃 )] | | 2𝐶 (5.20) (5.21) ⋮ 𝐶𝑅,𝑁+1 = [𝐶𝑅,𝑛+2 + (𝐶 + 𝐶𝑃 )] | | 2𝐶 (5.22) 𝐶𝑅,𝑛 = [𝐶𝑅,𝑛+1 + (𝐶 + 𝐶𝑃 )] | | 2𝐶. (5.23) Nodal parasitics primarily affect the INL of the design, as they are assumed to be uniformly distributed. The maximum INL can be found by integrating the difference of Vout to an ideal ramp over all input codes. Maximum INL for a C-2C array is plotted as a function of the size of Cp, relative to C, in Figure 5.7. For a typical value of parasitic (e.g., 3-5% of C), the INL is only less than 1 LSB for array resolutions of ~7b. The calculated INL for a 10b array is plotted as a function of the input code and compared to an ideal simulation in Figure 5.8. Cp is set at 5% of the branch capacitance, and the simulation shows an INL of ~11 LSB (e.g., loss of 3-4b). Simulation and theoretical calculations match well. 5.3.2 Mismatch An additional limitation on the accuracy of the split array, C-2C SCPA is related to the matching between the capacitors, which sets another limit on the INL and DNL that is achievable. INL and DNL depend on both the final DAC resolution, B, and element matching, 𝜎𝐸 , which can be expressed as follows: 𝜎𝐸 = 𝐾 √𝐴𝑟𝑒𝑎 (5.24) 68 K is a process parameter (e.g., 0.86 for the 65nm CMOS process used in this work). The INL/DNL can be calculated for the C-2C array and unary array separately to determine the matching accuracy required in the capacitors to achieve the designed resolution. The maximum allowed capacitor mismatch for the unary capacitors can be calculated using the following expressions [46]: 𝜎𝐼𝑁𝐿 = 𝜎𝐷𝑁𝐿 = 𝐼𝑁𝐿 √2(𝑒𝑟𝑓𝑖𝑛𝑣(𝑌)) 𝐷𝑁𝐿 √2(𝑒𝑟𝑓𝑖𝑛𝑣(𝑌)) 𝜎µ_𝐼𝑁𝐿 = 𝜎µ_𝐷𝑁𝐿 = 2𝜎𝐼𝑁𝐿 (5.25) (5.26) (5.27) √2𝐵 𝜎𝐷𝑁𝐿 (5.28) √2𝐵 −1 B is the number of bits, Y is the confidence interval (e.g., 95%), erfinv is the inverse error function, and 𝜎µ_𝐼𝑁𝐿 and 𝜎µ_𝐷𝑁𝐿 are the standard deviations of the capacitance mismatches. INL and DNL typically are desired to be less than one LSB at the designed resolution. The array is segmented with a 6b unary array; hence, 𝜎µ_𝐷𝑁𝐿 <6.4% and 𝜎µ_𝐼𝑁𝐿 L<12.6%. Even minimum area MiM capacitors in the process can easily meet these matching limits. For the C-2C array, the nodal parasitic dominates the INL. However, mismatch does have a significant impact on the DNL, which can be calculated as follows: 𝜎µ_𝐷𝑁𝐿 = 2𝜎𝐷𝑁𝐿 2𝐵 . (5.29) The calculated acceptable standard deviation for the unit capacitance is < 1.5%, which requires a capacitor of only 3 µ𝑚2 . It is noted that at the designed resolution for the unary array and the C-2C arrays, nodal parasitics limit the response more than mismatch. It is also noted that the total capacitance in the SCPA array is chosen to satisfy the desired network quality factor from (5.8), based on the desired output power from (5.2). 69 For the designed PA, the unit capacitance is ~40 µ𝑚2 , resulting in a mismatch of 0.14%, which is a significantly smaller mismatch than is required to meet the INL and DNL limits as calculated above. 5.4 Circuit Design Details A 16b, 16 phase SAMP-SCPA (Figure 5.9) was chosen for implementation, where the array was segmented into a 10b C-2C LSB subarray and a 6b unary MSB subarray. Though the C-2C is only accurate to ~7b, extra states in the C-2C array allow for digital calibration or DPD. Given the area, the unary array could be scaled to increase the total resolution up to the presented limits. Details of the design follow. 5.4.1 Top Level of the 13-b SAMP-SCPA A block diagram of the proposed differential 16b, 16-phase SAMP-SCPA is shown in Figure 5.9. The capacitor arrays are designed using MiM capacitors with layout techniques similar to those found in [47], as shown in Figure 5.10. This layout provides balanced parasitics at every node to minimize differential nonlinearities associated at every bit position in the C-2C arrays. It is also noted that an m-bit C-2C array scales linearly in area for each added bit, whereas an n-bit unary array scales exponentially in area with each added bit of resolution. Hence, the C-2C split array allows for an overall smaller design than a fully unary array would at the same output resolution. The array is designed to offer extra states that can be used for linearization, enabling the array to meet signal fidelity requirements for signals with large PAPR (e,g., EVM, ACLR, etc.). Amplitude and phase control bits are generated by a high-speed digital I/O with a clock rate of 100 MHz. To 70 minimize the number of digital I/O pads on the chip, the 36 control bits are serialized at a rate of 8:1. The digital pattern is input to a 1:8 deserializer. The 4 LSB bits are used to control the clock selection MUX, while the 32 MSBs control the multiphase logic decoder. In the proposed design, 16 evenly distributed phase vectors (𝜑1 − 𝜑16) are created by an off-chip phase generator. The details of individual blocks will be discussed as follows. 5.4.2 Unit Cell 5.4.2.1 Switch and Logic Design A cascode CMOS inverter serves as the output switch for the capacitor array (Figure 5.10, upper left). This permits the switch output voltage to be as high as 2× 𝑉𝐷𝐷 without exceeding the breakdown voltage rating of the transistors. This choice allows an increase in the output power that helps to reduce losses due to impedance transformation in the matching network [38]. The cascode inverter (Figure 5.10, upper left) is designed such that the gates of the inner transistors of the inverter are tied to VDD, while the outer transistors in the cascode are switched by time aligned nonoverlapping clock signals with different logic levels. Nonoverlapping signals allow crowbar current from VDD to VGND to be minimized, realizing a tri-state circuit. The NMOS transistors are switched by logic levels from VGND to VDD, while a level shifter is used to change the logic levels for the PMOS transistors to switch between VDD and 2VDD. The switch design is optimized to drive the input capacitance using sizing for logical effort to drive the desired capacitance. 71 5.4.2.2 Capacitor Design The capacitors are designed on the MiM layer and are sized based upon the chosen network quality factor (e.g., QNW=3) and the output power requirements, as dictated in (5.2) and (5.6). Equation (5.6) gives the total array capacitance, and then a unit cell is designed such that the unit cell capacitance is equal to the total capacitance divided by the number of unary bits. A layout of both the unary capacitor cell and C-2C capacitors is shown in Figure 5.10. The layout shows both the top view and the cross-section to detail the parasitic reduction efforts at the cell layout level. The capacitors are laid out between layers M7 and M8 using a mezzanine MiM layer. All unary capacitors share a common bottom plate that forms a ring around the top plate to minimize fringing capacitance between adjacent bits. The C-2C array is designed such that alternating inputs to the array are on either metal 7 or metal 8, to balance the parasitic between inputs. 5.4.3 Switch Driver Slice Design The driver slice for each capacitor cell is shown in Figure 5.11. Each slice consists of a phase selection 2:1 MUX that selects the phase of the clock to switch from and is followed by an OR gate that controls whether the slice is enabled (e.g., switches at the clock rate) or is held at ground. Because the two phases that are routed to each cell propagate at the same frequency, clock routing can be matched using a standard H-tree distribution to each cell. No additional calibration is necessary, as each cell is designed to present the same load to the clock tree. A chain of inverters is sized using to provide delay matched switching signals to 72 drive the cascoded output switch that is connected to a capacitor in the array. The slice is designed to be pitch matched to the capacitor it is driving in the array for maximal layout compactness. The PMOS and NMOS switches in the output stage switch are driven from separate supply ranges to protect the devices from the 2VDD supply swing. A level shifter [113] is used to change the supply domain for the PMOS switches to operate between VDD and 2VDD, while the NMOS switches operate between VGND and VDD. Simulations are run to ensure that the timing in the separate PMOS and NMOS paths match well. It is noted that all capacitors in the unary array are identical; hence, all devices in the unary slices are sized equally. The input capacitance in the C-2C slices varies by bit position; hence, each element in the C-2C array is optimized to match the delay in the unary array paths. Note that the logic that enables and disables each slice is changing at the modulation rate, which is significantly slower than the clock rate, and hence jitter limitations are not considered in this design. 5.4.4 Phase Selector and Amplitude Decoder Logic The deserializer, phase selection logic, and MP decoder logic are designed in Verilog and synthesized using a standard cell library. The decoders control a total of 68 billion output states. The deserializer is designed as a set of parallel 8b shift registers, and the outputs are segmented on chip before being input to the clock selection logic or multiphase decoder logic. The 16 evenly distributed phases are input to the clock selection logic, which is 73 comprised of logic selection bits controlling MUX tree decoder. The two adjacent phases to the desired output phase (e.g., 𝜑𝐴 , 𝜑𝐵 𝑎𝑛𝑑 𝜑̅𝐴 , 𝜑̅𝐵 ) are chosen by the MUX and passed to the multiphase logic decoder. The multiphase logic decoder comprises a cascade of two binary-to-thermometer (B-T) decoders. The first 16b (B-T) decoder controls how many cells are switched by phase 𝜑𝐴 (𝜑̅𝐴 ). The second 16b (B-T) decoder controls whether the balance of cells are switched by 𝜑𝐵 (𝜑̅𝐵 ) or held at ground. The synthesized decoders are designed to match the timing in each bit path to minimize mismatch in the enable/disable delays and phase selection for each cell. 5.4.5 Matching Network The matching network that transforms the antenna impedance of 50 Ω to the optimum termination impedance consists of a shunt symmetric inductor, 𝐿𝑠ℎ , a series inductor, 𝐿𝑠𝑒𝑟 , and a shunt capacitor, 𝐶𝑠ℎ , forming a bandpass resonant circuit at the design frequency. This network is chosen to provide a high impedance path toward the output to minimize the output contribution from high frequency harmonics. Because the total capacitance seen by the matching network remains constant, regardless of the number of capacitors being switched, it can be sized to be resonant with the total array capacitance and remains unchanged for any choice of input code. The value of the loaded quality factor is chosen to be ~3, leading to a circuit with >600 MHz -3-dB bandwidth centered at around 1.8 GHz. If off-chip impedance transformations are used, higher quality factors can be chosen. The experimental results of the prototype SAMP-SCPA are now discussed. 74 5.5 Experimental Results The prototype MPSA-SCPA is fabricated in a 65 nm RF CMOS process with ultrathick top metal for high quality passive components. The chip microphotograph is shown in Figure 5.12. It occupies a total area of 0.85 mm×2 mm, including the matching network, output stage, logic decoders, and all of the I/O pads for supply and data. The C-2C SASCPA is implemented as an MP-SCPA, as shown in Figure 5.9. The core logic for this process runs at 1.2V, allowing the cascoded output stage to operate at 2.4 V. The measurement setup can be seen in Figure 5.13. Sixteen phase vectors generated by an offchip phase generator and received on-chip using low-voltage differential signaling (LVDS) amplifier are input to the clock selection logic. Due to the large numbers of digital I/O on this chip, the control bits are serialized to minimize the required pads. In system-on-chip (SoC) operation, serialization is not necessary, but it can be used to reduce wiring busses. 5.5.1 Static Measurements Shown in Figure 5.14 is the measured static output power, Pout, and system efficiency (SE) versus frequency. It is noted that the SE is the ratio of Pout to all input (DC and RF) power to the chip, including pad drivers. Operating at a center frequency of 1.8 GHz, the SAMP-SCPA outputs a peak power of 24 dBm with a peak SE of 40%. The measured -3-dB output power bandwidth of the PA is 700 MHz, which is determined by the loaded quality factor of the band-pass matching network. The power consumed in each major block is broken down in Figure 5.15. The measured and simulated Pout with and without bondires is plotted as a function of the digital input code at 1.8 GHz in Figure 5.16. The simulation with estimated bondwire inductance matches well with the measurement. 75 The simulated drain efficiency and measured and simulated SE (w/ bond wire effects) is plotted versus output power in Figure 5.17, showing good agreement between simulation and measurement. The output power displays a weak nonlinearity due primarily to supply inductance, with some INL contribution from parasitic capacitance in the C-2C array. This can be mitigated with low-inductance packaging (e.g., flip-chip or wafer level chip scale packaging). The AM-AM and AM-PM before and after DPD are shown in Figure 5.18 and Figure 5.19, respectively. 5.5.2 Dynamic Measurements To verify the SAMP-SCPAs performance with signals with large PAPR, it is tested with a 1.4 MHz, 64 QAM LTE signal. The nonlinearity from supply and ground bondwire inductance and any mismatch/parasitic effects are corrected with a polar digital predistortion (DPD) [10]. The ACLR performance at maximum output power is plotted in Figure 5.20. The DPD is optimized to meet the E-UTRA ACLR specification for an uplink signal of < -30 dBc. The signal is detroughed to reduce the PAPR down to the ACLR limit. Detroughing can be tradedoff for better ACLR at the expense of reduced efficiency. The transmitted power at this ACLR is 18.8 dBm with an average SE of 21.6%. The measured EVM at this output power is less than 2.65 %-rms. Due to the versatility of the SAMP-SCPA, output power can be traded off for improved linearity. When adjusting the input code to slightly less than half power and using polar DPD, the ACLR is < -37 dBc (Figure 5.21) when outputting 14.6 dBm. The LTE constellation is plotted in Figure 5.22 for maximum output power and Figure 5.23 at reduced output power when optimized for the lowest EVM. The 76 constellation shows improved EVM as power is traded off for linearity. The SAMP-SCPA is a quantized system; therefore, the OOB noise is dominated by signal quantization. The OOB noise for the 16-bit C-2C SAMP-SCPA when transmitting a 1.4 MHz, 64 QAM LTE signal compared with the previous work at lower resolution is plotted in Figure 5.24. The PSD demonstrates a out-of-band noise for a DAC with an ENOB of ~13b [114]. To minimize the space required for digital I/O pads, the input bits are serialized at 8:1; the HSDIO utilized offers a maximum clock rate of 100 MHz, resulting in a bit rate of 12.5 MHz input to the chip. This limits the maximum signal bandwidth; it is expected that without this limitation the bandwidth performance would be similar to other implementations of the SCPA [38], [33], and [41]. Due to the I/O and instrument limitation, the switching spurs are closer in; however, the overall noise floor of the SAMP-SCPA achieves an SNR expected for an ENOB of ~13b. 5.6 Summary Split-array SCPA techniques are introduced and implemented in a prototype SAMP-SCPA in 65nm CMOS. The concept of multiphase signaling is used to leverage the advantages of DPAs while not requiring the wideband phase modulator of polar DPAs, or having the high combining loss of quadrature DPAs. When operating at 1.8 GHz, this PA delivers a peak Pout of 24 dBm with 40 % SE. The performance is validated from static and modulation measurements using a 1.4 MHz, 64-QAM LTE signal. With polar DPD, the ACLR is below the required -30 dBc LTE standard and the measured EVM is 2.65 %-rms. A comparison to prior art is provided in Table 5.1. The SAMP-SCPA is compared to prior MP DPAs [41], quadrature DPAs [32], [33], as well as polar DPAs [37], [115-117]. SAMP- 77 SCPA achieves similar output power and SE to prior art in digital PAs, while offering reduced OOB noise. The SAMP-SCPA is not just a PA, but a versatile digital TX front end. 78 Figure 5.1. Split-array SCPA schematics: (a) traditional binary/unary split-array; (b) C2C/unary split-array. 79 . Figure 5.2. SCPA total efficiency versus loaded network quality factor. Figure 5.3. Examples operation of a MP-SCPA with 16 phases SCPA. 80 Figure 5.4. Normalized output power versus code for different number of phases, M. Figure 5.5. FoM versus bit position of the array split for different SA-SCPA configurations. 81 Figure 5.6. C-2C DAC with nodal parasitic. Figure 5.7. Maximum INL versus 𝐶𝑃 of a C-2C array for different resolutions. 82 Figure 5.8. Calculated versus simulated INL for 10-bit C-2C array with 5% 𝐶𝑃 . Figure 5.9. Block diagram schematic of the prototype 13-b, 16-phase C-2C SAMP-SCPA. 83 Figure 5.10. Capacitor layout and cross-section for the unit unary cell and C-2C array. Figure 5.11. Block diagram of the slice enable and phase selection logic. 84 Figure 5.12. 65nm experimental prototype SAMP-SCPA chip microphotograph. . Figure 5.13. Measurement setup for static and dynamic measurements. Note that all instruments reside in a single NI-PXI chassis. 85 Figure 5.14. Measured output power and SE versus frequency. Figure 5.15. Simulated ouput power breakdown of the output stage, slice logic, and PA drivers and input decoders and pad drivers. 86 Figure 5.16. Measured and simulated output power versus code at 1.8 GHz. Figure 5.17. Measured and simulated SE and drain efficiency versus output power. Figure 5.18. AM-AM distortion versus codeword before and after DPD. 87 Figure 5.19. AM-PM distortion versus codeword before and after DPD. Figure 5.20. Measured ACLR for a 1.4 MHz, 64 QAM LTE signal at optimized for maximum output power. 88 Figure 5.21. Measured ACLR for a 1.4 MHz, 64 QAM LTE signal at optimized for EVM. 89 Figure 5.22. Constellation for 1.4 MHz, 64-QAM LTE at maximum output power (2.65%-rms). . Figure 5.23. Constellation for 1.4 MHz, 64-QAM LTE at 4.3 dB backoff (2.65%-rms), optimized for lowest EVM. 90 RFIC 2016 This Work Noise Floor Figure 5.24. Measured PSD of the 13b SAMP-SCPA. 91 Table 5.1. Comparison of prior art. This Work [33] [32] [41] [37] Process technology 65 nm 65 nm 65 nm 130 nm 65 nm Supply voltage (V) 2.4 1.2/2.4 1.3 3 1.2 Resolution (bit) 13-MP 9-IQ 13-IQ 7-MP 9-Polar Carrier Frequency 1.8 GHz 2.0 GHz 2.4 GHz 1.8 GHz 2.2 GHz Peak Pout (dBm) 24 20.5 22.8 26 23.3 PAE at peak Pout 40 % 20 % 42 % 24.9 % 38 % Modulation signal LTE 1.4 MHz, 64-QAM LTE 10 MHz, 64-QAM Single carrier 22 MHz, 64QAM LTE 10 MHz, 64-QAM 802.11g 20 MHz, 64QAM Average Pout (dBm) 18.9 14.5 15 20.9 16.8 Average PAE 21.2 % 12.2 % NA 15.2 % 21.8 % EVM ( %) 2.65 %-rms 3.6 %-rms 3.98 %-rms 3.5 %-rms 3.98 %-rms ACLR (dBc) -30.5/-30.9 -30.7/-31.0 <-43 dBc -30.3/31.7 NA Matching Network On-Chip On-Chip Transformer On-Chip Transformer CHAPTER 6 A MULTIPHASE INTERPOLATING DIGITAL POWER AMPLIFIER FOR TX BEAMFORMING 6.1 Introduction In recent years, there has been tremendous growth in research into data transmission capacity improvement for wireless communication system, especially for future 5G. Phased-array transmitter can leverage spatial diversity or SNR enhancements to increase wireless channel capacity. In a TX beamformer, the amplitude and phase of the signal being transmitted on each array of TXs can be set accurately to spatially steer the beam toward a user, or multiple users. Therefore, the TX beamformer with precise amplitude scaling, accurate phase shift, and high system efficiency (SE) are essential. Traditional analog TX beamforming topologies [118-120] can be grouped into LO phase-shifting, IF phase-shifting, and RF phase-shifting architectures depending on the positon of the phase shifters in the TX chain. The time delay of LO phase-shifting architecture cannot be applied to the modulated signal, so for very wideband signals some distortion will be introduced. IF phase-shifting architecture consumes much power and the area due to increased duplication (each antenna path requires a dedicated mixer for the down-conversion to IF), and the phase shifters themselves will be larger since the passive components required in a phase shifter scale in inverse proportion to the frequency of 93 operation. Although RF phase-shifting architecture consumes minimal power since only phase shifters must be duplicated, and the IF and baseband stages can be shared between all signal paths, the nonlinearity of the phase shifter in RF path has serious effects upon the TX performance. Traditional digital TX beamforming [121] is an attractive option from a flexibility standpoint and its capacity for multiuser beamforming. It allows multiple beams to be formed and directed to an arbitrary number of users. However, the extensive digital beamforming signal processing tends to be large and high power consumption. In recent beamforming TXs, four primary means to control the output beam angle have been leveraged. Passive RF phase shifting is bulky and lossy, owing to high losses in the passive elements, and it is difficult to provide phase control through 360°. LO phaseshifting often uses a single passive phase shifter, or a multiphase ring oscillator; these typically provide lower phase resolution. Digitally controlled delay lines provide a wider bandwidth response but suffer from reduced phase resolution as frequency is increased and can consume high power [48]. Digital phase shifting techniques have recently shown promise in polar systems [49], [50], but the quadrature modulator typically used for phase shifting incurs high loss if placed directly at the output stage. In this work, I propose a multiphase controller to directly control a power amplifier (PA) allowing for high phase/gain resolution with reduced loss by performing a vector addition of the beam phase and amplitude. A C-2C split-array multiphase switchedcapacitor PA (SAMP-SCPA) [44] is implemented in each TX chain to overcome the challenges of simultaneously designing SCPAs with high resolution and high output power, and they do not suffer from the requirement for high bandwidth amplitude and/or phase 94 modulators and the bandwidth expansion involved with polar conversion [69] dominating the overall nonlinearity. A 4-element digital modulated multiphase phased-array TX in 65nm CMOS is designed and fabricated to demonstrate the prototype, which to our knowledge is the first of its kind. It can achieve < 1° phase resolution and <1 dB gain error with the 9-bit RF-DAC while obtaining 24.4 dBm peak output power and 24% peak SE with no digital predistortion (DPD). 6.2 Theoretical Operation of C-2C SA-SCPA Traditional SCPA, using polar modulation, are special cases of the Class-D PA, where the capacitor in the series resonant output network is subdivided into an array of smaller unit capacitors that are driven by independent switches, shown in Figure 6.1a. It can achieve high energy efficiency when amplifying waveforms with high PAPR [38]. In SCPA, the top plate of a number of unit capacitors are connected, while the other plate of each capacitor in the array is driven by an independent switch and driver chain that can be either switched at the RF carrier frequency or held at ground. The primary problem with all SCPA architectures has been their relatively low resolution, resulting in large out-ofband (OOB) noise. In a split-array, the total capacitor array can be divided into two or more subarrays with larger unit capacitor using an attenuation capacitor, CA, as shown in Figure 6.1b, which is added between LSB subarray and MSB subarray to balance the charge between the arrays. Therefore, seen from MSB subarray perspective, the capacitance is always equal to the value of the smallest capacitor in the MSB subarray. This method can mitigate the challenge of designing small MiM capacitors or using lossier, more parasitic laden vertical 95 natural capacitors. Additionally, the ratio of the largest and smallest capacitance can be tightly controlled to be small to reduce the effect of the mismatch between capacitance. The position of CA can be varied from LSB subarray to MSB subarray, which influences the size of arrays, input power consumption, and linearity. Considering the factors mentioned above, C-2C LSB subarray and unary MSB subarray combination is chosen. This is because the size of the C-2C array increases linearly with the resolution, thus occupying less area then a binary-weighed array. C-2C segmented arrays preserve the area efficiency benefits as they use the same number of unit cells as binary segmented arrays. Moreover, the ratio between the maximum and minimum capacitance is only two, which reduce the effect of the mismatch between capacitance and provide better matching in the layout since the entire topology is composed of the replicas of a small C-2C block. A C-2C SA-SCPA design begins by choosing Ropt to provide the desired output power. Because of the band-pass nature of the structure, only the fundamental component at the RF carrier frequency flows to the output: 𝑉𝑜𝑢𝑡 = 2 𝑛 𝜋 𝑁 𝑉𝐷𝐷 (6.1) where 2/ 𝜋 is the Fourier coefficient for the fundamental frequency of the square switching wave, 𝑛 is the number of unit capacitors whose bottom plates are switched between 𝑉𝐷𝐷 and 𝑉𝐺𝑁𝐷 , 𝑁 is the total number of capacitors, and 𝑉𝐷𝐷 is the voltage switched at the bottom plates. The output power is given by the square of the RMS value of the output voltage, divided by the load resistance it is driving, Ropt: 𝑃𝑜𝑢𝑡 = 2 𝜋2 2 𝑛 2 𝑣𝐷𝐷 (𝑁) 𝑅𝑜𝑢𝑡 . (6.2) The input power is due the power dissipated in charging and discharging the total input capacitance to its final voltage: 96 2 𝑃𝑖𝑛 = 𝐶𝑖𝑛 𝑣𝐷𝐷 𝑓0 (6.3) where 𝐶𝑖𝑛 is the input capacitance that varies with the selected input code, n, and 𝑓0 is the RF carrier frequency. Cin is given as 𝐶𝑖𝑛 = 𝑛(𝑁−𝑛) 𝑁2 𝐶𝑡𝑜𝑡 (6.4) 𝐶𝑡𝑜𝑡 is the total capacitance in the array. The size for the LSB subarray and MSB sub-array are given as follows: 𝐶𝑈 = 𝐶𝑈,0 = 𝐶𝑈,𝑀 = 𝐶𝑡𝑜𝑡 2𝑀 𝐶𝐿𝑆𝐵,𝑡𝑜𝑡 = 2𝐶𝑈 (6.5) (6.6) 𝐶𝑀𝑆𝐵,𝑡𝑜𝑡 = 𝐶𝑈 (2𝑀 − 1) (6.7) where 𝐶𝑈 is the unit capacitance in the C-2C LSB subarray, and 𝐶𝑈,0 and 𝐶𝑈,𝑀 are the unit capacitance in the unary MSB subarray, as shown in Figure 6.1b. M is the number of bit in unary MSB subarray, and 𝐶𝐿𝑆𝐵,𝑡𝑜𝑡 and 𝐶𝑀𝑆𝐵,𝑡𝑜𝑡 are the total capacitance in C-2C LSB subarray and unary MSB subarray, respectively. The attenuation capacitance be can expressed as follows: 𝐶𝐴 = 𝐶𝑈 𝐶𝐿𝑆𝐵,𝑡𝑜𝑡 𝐶𝐿𝑆𝐵,𝑡𝑜𝑡 −𝐶𝑈 = 2𝐶𝑈 . (6.8) The size of the switches driving C-2C LSB side and unary MSB side is different because the total capacitance seen by the LSB switches increases as the resolution improves. Therefore, the size of both subarrays should be optimized to minimize the switching loss and delay differences. The method of logical effort is used to calculate the size of the switches, while optimizing the delay versus switching power consumption tradeoff. Even though the size of unit capacitance in C-2C LSB subarray is the exactly same as that in unary MSB subarray to reduce the effect of mismatches between the capacitors, the 97 resolution limit of C-2C array still dominates the overall linearity of the C-2C SA-SCPA, which is determined by mismatch due to PVT variations of the capacitors in the array parasitics between internal nodes and the substrate and the jitter limitation of the clock. For more details on the analysis of the limitation of the C-2C array, the reader is referred to [44]. 6.3 Multiphase Interpolation Beamforming Multiphase SCPA (M-SCPA) [41] is the core part for multiphase interpolation beamforming. The operation of the conventional polar SCPA requires a coordinate rotation digital computer (CORDIC) to convert the I and Q signals into amplitude and phase, which results in bandwidth expansion of both amplitude and phase due to nonlinear conversion form Cartesian to polar coordinate system. Moreover, conventional phase modulators are implemented using phased-locked loop (PLL) and have a narrow bandwidth, which is not suitable for wideband modulation techniques. Though open-loop phase modulation is alternative, it suffers from phase quantization noise and digital-to-phase nonlinearity, which adds more complexity to entire system. Additionally, the amplitude and phase signal propagate at different frequencies on separate paths, resulting in a significant delay mismatch, which can cause spectral mask violation for modulated signals. Therefore, multiphase interpolation beamforming is proposed to directly control the output stage and allow for high phase resolution with reduced loss by performing a vector addition of the beam phase at the output. The details will be discussed as follows. 98 6.3.1 Number of Phase Selection in TX Beamforming Due to the nonoverlapping region of I/Q clocks, the output power of M-SCPA will be loss compared with polar SCPA. This nonoverlapping region is critical for the generation of output signals with arbitrary phases. As shown in Figure 6.2a, for an arbitrary vector (A,θ), it can be converted to multiphase domain using following equations: 𝑛1 = 𝐴𝑐𝑜𝑠( 𝜋 𝑀 𝑛2 = 𝐴𝑐𝑜𝑠( 2𝜋 ) 𝑀 2𝜋 sin( −𝜙) 𝑀 sin( ) 2𝜋 ) 𝑀 sin( 𝜋 ) 𝑀 𝜙= 𝜃− (6.10) sin(𝜙) 2𝜋 𝑀 (6.9) 𝑚 (6.11) where 𝑛1 and 𝑛2 represent the amplitudes of the selected adjacent two phase vectors, 𝑀 is the number of phase, and 𝑚 is an integer, representing the index of the selected phase vector that is determined by 𝑚 𝑀 𝜋≤ 𝜃< 𝑚+1 𝜋. 𝑀 (6.12) In general, the power loss at phase 𝜙 of the M-phase architecture compared with that of the polar architecture can be calculated by 𝑃𝑙𝑜𝑠𝑠,𝑀𝑃 = A(𝜙)2 (𝑛1 (ϕ) + 𝑛1 (ϕ))2 = sin2 (π− 2π ) M . (6.13) = cos 2 (π/M). (6.14) (|sin( 2𝜋 −𝜙)|+ |𝑠𝑖𝑛𝜙|2 𝑚 When θ = π/M, the maximum power loss shows as follows: 𝑃𝑙𝑜𝑠𝑠_𝑚𝑎𝑥,𝑀𝑃 = A(𝜋/𝑀)2 (𝑛1 (𝜋/𝑀) + 𝑛1 (𝜋/𝑀))2 The average output power for a uniformly distributed phase signal over the range from 0 to 2π is given by 𝑃𝑙𝑜𝑠𝑠𝑎𝑣𝑔 ,𝑀𝑃 = (M−2)π sin2( ) 2𝜋 M 𝑑𝜙 ∫ 2𝜋 2𝜋 0 (|sin( −𝜙)|+ |𝑠𝑖𝑛𝜙|2 1 𝑚 = (M−2)π ) M 2π 2𝜋(1−𝑐𝑜𝑠 ) M Msin2 ( π tan(M ). (6.15) 99 Table 6.1 shows that increasing the number of phases can decrease the power loss in multiphase architecture. It behaves like a polar SCPA if the number of phase goes infinite. The normalized output power can be expressed in below: 𝑃𝑜𝑢𝑡,𝑛𝑜𝑟𝑚𝑎𝑙𝑖𝑧𝑒𝑑 = 2𝜋 ) 𝑀 𝑛12 + 𝑛22 +2𝑛1 𝑛2 cos( 4𝑁 2 (6.16) The normalized output power versus the input code for 9-bit array and the number of phases is illustrated in Figure 6.3. It is shown that the output power increases dramatically from M=4 to M=8 and also from M=8 to M=16. However, there is no significant jump when increasing the number of phase beyond 16. Another factor in choosing the number of phase is that with the increasing number of phase, there is less time available for setting between edges so that the distortion between phases would cause nonlinearity. As shown in Figure 6.2b, the charge should settle on each capacitor that is switched on phase m before the beginning of phase m+1. Therefore, 16 phases are chosen based on the settling limit and the lack of significant improvement in output power. 6.3.2 Operation of Multiphase Interpolation Beamforming Figure 6.4 shows the concept of the 4-element multiphase beamforming TX system. A set of constant evenly spaced phases (ϕ1 - ϕM ) that span the unit circle, which can cover 3600 when steering the beam, is generated by a multiphase clock generator, weighted, and summed to provide amplitude/phase modulation data from the input. This can be accomplished by using an MP ring oscillator, polyphaser filters, or delay-locked loops (DLLs). Clock selection logic, implemented as a MUX tree, selects the two output adjacent phases (ϕA and ϕB ) that are closest to the desired modulation phase. The phases, ϕA and ϕB , are distributed to every cell of a N-bit capacitor array in SAMP-SCPA. Therefore, the 100 multiphase logic decoder comprises two sets of thermometer decoders with 2N-bit. The first N-bit thermometer decoder decides how many unit capacitor to be driven by ϕA . While the second N-bit thermometer decoder decides whether the rest of unit capacitor to be driven by ϕB or held at ground. Unlike [49], which only applies digital phase shifting using digital phase shifter, we combine the amplitude weighting and phase shifting in a signal multiphase logic decoder, which can save a lot of power and area. A control bit in multiphase logic decoder is significant for amplitude weighting and phase shifting. If it is enabled, the information of amplitude and phase can be converted to multiphase information by multiphase logic decoder. A coarse phase shift can be achieved based on the two adjacent phases (ϕA and ϕB ) out of 16 basis phases. Then adjusting the number of unit capacitors switching in I and Q mode, the output with desired amplitude weighting and phase shifting can be obtained and stored. Therefore, multiphase interpolation for fine phase shift is achieved. If the control bit is disabled, the digital modulated signal can be transferred to multiphase logic decoder to get modulated output based on different preset amplitude weighting and phase shifting for each PA. The operation of multiphase interpolation beamforming is implemented in a single multiphase logic decoder. Moreover, each TX beamforming chain has an independent multiphase logic decoder, which can do beam weighting individually. When combining the output with four different amplitudes, the nonequal amplitude weightings are important because it will have a large rejection of unintended signals at the expense of a small decrease in gain. An example for 16 basis phase vectors that are available for recombination is shown in Figure 6.5. In polar SCPA, the input pulse waves for all the capacitors are the same. Instead of using the same phase modulated pulse wave, two separate pulse waves that are 101 22.5 degrees out of phase are used. Each capacitor in the capacitor array can be switched by a pulse wave with any one of the 16 phases. Therefore, each phase can be weighted and summed in the charge domain to output the desired amplitude and phase. Making ϕ0 as the reference, in Figure 6.5a, the phase shift is 45 degrees, and the amplitude is the largest as all the capacitor are switched in that direction. Shown in Figure 6.5b, ϕA and ϕB are chosen to get the desired 168.750 phase shift with lower amplitude. The two adjacent pulse waves are fixed in phase in the Cartesian coordinates, and an arbitrary vector with amplitude and phase can be converted into the multiphase domain. By choosing which two adjacent pulse waves to be used and how many capacitors to be switched, any desired beam can be achieved to steer to any direction. 6.4 Circuit Design Details Figure 6.5 illustrates the proposed 4-channel beamforming TX, which is comprised of four identical SAMP-SCPAs. SAMP-SCPA achieves high linearity, constant load, compact size, and the ability to output high power with high efficiency, while offering reduced OOB noise, which can get high phase shift resolution. Each SAMP-SCPA has a local multiphase ring oscillator to create 16 evenly basis phases and injection locked to a common global clock. The clock is input to the chip via an LVDS clock RX. Care is taken to route the clock with equal delay to each ring oscillator to provide common time/phase basis. Details of each beamforming TX is discussed as follows. 102 6.4.1 Top Level of the 9-b SAMP-SCPA Each beamforming TX consists of an SPMP-SCPA. A block diagram of the proposed differential 9b, 16-phase SAMP-SCPA is shown in Figure 6.6. Multiphase clock generator creates 16 evenly spaced phases that input to the clock selection logic, implemented as a MUX tree. Four bits from the digital pattern generator are used to choose the two adjacent phases (ϕA and ϕB ) out of 16 evenly distributed phases of the desired output signal, which accomplish the coarse phase shift. Those two adjacent phases are distributed to every cell of a 9b capacitor array, where a 18b multiphase logic decoder decides how many capacitors are switched to ϕA , ϕB or held at ground. MiM capacitors are used in capacitor array. The top plates are shared to connect in series with output matching network, while the bottom plate are connected to the switch and control logic. The array is subdivided into a 5b C-2C LSB subarray and 4b unary MSB subarray. The choice of where to subdivide the array depends on the desired linearity and complexity of the thermometer decoder required for the unary weighted bits. The details of individual blocks follows. 6.4.2 Switch and Logic Design In order to provide large output impedance that can increase the output power and reduce the loss of matching networking simultaneously, a cascode CMOS inverter (Figure 6.6) acting as the switch between the doubled supply voltage, labeled as 2𝑉𝐷𝐷 , and ground are chosen. This topology allows the top transistor to have its gate oxide stress reduced by providing it a constant gate, which can mitigate tremendous stress on the gate oxide caused by input swing when using one single transistor. The region of NMOS switches operates 103 between 𝑉𝐺𝑁𝐷 and 𝑉𝐷𝐷 , while the region of PMOS switches operate between 𝑉𝐷𝐷 and 2𝑉𝐷𝐷 , using a level shifter [113] to achieve it and the gate voltage on the cascode transistors ( 𝑀𝑁2 and 𝑀𝑃2 ) are tied to 𝑉𝐷𝐷 . The switch design is optimized to drive the input capacitance using sizing for logical effort to drive the desired capacitance. 6.4.3 Switch Driver Slice Design The driver slice is located adjacent to the switch and takes its input from the decoder. Colocation of the logic and driving chains allows the parasitic routing capacitance to be minimized and for easier timing synchronization of the switching signals. A level shifter in the PMOS transistors path is used to change the logic levels to operate between 𝑉𝐷𝐷 and 2𝑉𝐷𝐷 . Inverters after the level shifters are placed in isolation wells to allow operation from these different supply rails. Therefore, a level shifter and separate buffer chains in each unit cell are used to drive the high-side 𝑀𝑃1 and low-side 𝑀𝑁1 of the switch. To avoid the conduction loss, the delay mismatch between 𝑉𝑃 and 𝑉𝑁 in two different paths should be minimized. Moreover, it can also mitigate the potential for crowbar current to flow between the supply rails if PMOS and NMOS paths are on simultaneously. In unary MSB subarray, all the unit capacitors in each path are exactly the same, so the size for every transistor in unary MSB path is identical. While in C-2C LSB subarray, the total equivalent capacitance for a C-2C array increase linearly as the number of C-2C bits are increased. Also, the nodal parasitic cannot be ignored when considering the total equivalent capacitance. Therefore, the size of the transistors in C-2C LSB path should be optimized to match the delay in the unary MSB path. 104 6.4.4 Phase Selector and Multiphase Decoder Logic Amplitude weighing and phase shifting are dominated by the control bit in multiphase decoder logic. When the control bit is enabled, the multiphase interpolation beamforming operates in two steps. First, two adjacent phases are chosen by clock selection MUX tree comprising a 4b synthesized decoder to control 16 evenly distributed phases. The coarse phase shift is achieved based on the two selected phases. Next, the multiphase logic decoder receives the 9b envelope code and 9b phase selection code that are embedded with both the envelope modulation and beam weighting. The decoder decides the number of capacitors to be switched on each phase of the selected clocks and provides the fine phase shift. When the control bit is disabled, modulation can be added to the stored beam output code. Two identical binary-to-thermometer consists the multiphase logic decoder. The first 9b binary-to-thermometer decoder selects how many cells are switched by phase ϕA . The second 9b binary-to-thermometer decoder selects whether the balance of cells are switched by ϕB or held at ground. All decoders are designed in Verilog, synthesized, and automatically placed and routed. 6.4.5 Matching Network The total capacitance in the array seen from matching network remains constant, regardless of the input code. Hence the matching network is unchanged for any choice of input code. The matching network is comprised of shunt inductor, 𝐿𝑠ℎ , a series inductor, 𝐿𝑠𝑒𝑟 , and a shunt capacitor, 𝐶𝑠ℎ , forming a band-pass network, series resonant with the total capacitance array, which filter high frequency harmonic due to switching. -3 dB output 105 power bandwidth is around 700 MHz, centered at around 1.8 GHz, which is determined by the loaded quality factor (~3) of the band-pass matching network. If off-chip impedance transformations are used, higher quality factors can be chosen. The experimental results of the prototype 4-element beamforming TX are now discussed. 6.5 Experimental Results The prototype of 4-element beamforming TX is fabricated in a 65 nm RF CMOS process with nine layers of ultra-thick top metal for high quality passive components. The chip microphotograph is shown in Figure 6.7. The combined area of all four TXs occupies five, including the matching network, output stage, logic decoders, and all of the I/O and supply pads; the chip area is heavily pad dominated due to required I/O. All circuits operate from 1.2 V, with the exception of the cascaded switches that operate from 2.4 V. The measurement setup can be seen in Figure 6.8. The TX array is chip-on-board bonded to a PCB, and an off-chip transformer balun converts the differential signal to single-ended to drive an SMP jack. Sixteen phase vectors generated by an off-chip vector signal generator and received on-chip using low-voltage differential signaling (LVDS) amplifier are input to the clock selection logic. A 4-bit phase logic from digital pattern generator selects two out of 16 clocks with adjacent phases for the desired output for coarse phase shift, while two 9-b thermal to thermometer decoders independently control the number of capacitors that are switched or held at ground to achieve fine phase shift. The modulation results are displayed from vector signal analyzer. Individual TXs are characterized for their static and dynamic (modulated) characteristics and beamforming measurements shown as follows. 106 6.5.1 Static Measurements The individual TX shows similar measured performance. The measurements consider all losses including off-chip balun and SMP connector. Shown in Figure 6.9 is the measured static output power, Pout, and system efficiency (SE) versus frequency with a peak output power and SE of 24.4 dBm and 24.2% at center frequency 1.75 GHz, respectively. The measured -3-dB output power bandwidth of the PA is 750 MHz, which is determined by the loaded quality factor of the band-pass matching network. Figure 6.10 and Figure 6.11 illustrate the measured output power versus the input code and measured SE versus output power at 1.6 GHz, 1.75 GHz and 1.9 GHz, respectively. The output power versus input code displays a weak nonlinearity due to the bondwire inductance, capacitor mismatch, and difference of the adjacent clock. Note that the SE includes all power inputted to the chip, including pad drivers. 6.5.2 Dynamic Measurements To verify the individual TX performance with signals with large PAPR, it is tested with both a polar modulation (injection clock is phase modulated) with 15 MHz, 64 QAM LTE signal and a multiphase modulation (injection clock is not modulated) with 10 MHz, 64 QAM LTE signal, shown in Figure 6.12 and Figure 6.13. The measured ACLR and EVM at the center frequency are <-30dBc and 3.27%-rms for polar mode and <-30dBc and 3.13%-rms for multiphase-mode without use of digital predistortion (DPD). EVM and ACLR are maintained across the band without use of DPD. 107 6.5.3 Beamforming Measurements To verify the performance of the TXs as a function of the beam-steering angle, the phase error and output power versus phase are measured for four TXs on a single die in Figure 6.14 and Figure 6.15, respectively. An off-line calibration is used to correct the static phase output and the phase error after calibration is ±1° across the 9b code range, with a phase error <0.32°-rms, across all four PAs. The output power varies by <1dB for outputs across the code range, with output power error <0.15dB-rms, across all four PAs. The beam angle is synthesized using measured data for several pointing directions for a linear array with /2 spacing and compared to the ideal synthesized beam angle in Figure 6.16. The synthesized beam from measured data matches well with the ideal synthesized beam across all output phases. 6.6 Summary A 4-element beamforming TX is introduced and implemented in 65nm CMOS. The concept is to use multiphase interpolation for beam-steering and leveraging the SCPA to simultaneously realize high linearity, power and system efficiency with a small die area. When operating at 1.75 GHz, all four TXs can deliver a peak Pout of 24.4 dBm with 24.2 % SE while achieving < 1° phase resolution and <1 dB gain error. The performance is validated from static and modulation measurements using both polar mode and multiphase mode without use of DPD. The ACLR is below the required -30 dBc LTE standard for both mode and the measured EVM is 3.27 %-rms and 3.13 %-rms, respectively. A comparison to prior art is provided in Table 6.2. Compared to [49], which is the most closely related work, the proposed work achieves similar phase and amplitude resolution, 108 but at higher output power and without the use of DPD, while achieving better linearity (ACLR and EVM). Also, beam amplitude weighting is natively included in the proposed work. Due to the compact size of the SCPA, it also uses less chip area. Because of the relatively high output power and small area, this can be deployed in massive-MIMO systems that require a dense array with lower radiated power per element, without the requirement of an external PA. 109 Figure 6.1. Schematic of capacitor combination. (a) Traditional unary/binary split-array SCPA; (b) C-2C/unary split-array SCPA. 110 Figure 6.2. Example of 16 phases. (a) Polar to multiphase conversion; (b) 4 of 16-phases in time domain. Figure 6.3. 10-bit normalized output power versus code for different number of phases. 111 Figure 6.4. Multiphase beamforming TX concept. 112 Figure 6.5. Examples operation of multiphase beamforming TX with 16 phases. 113 Figure 6.6. Schematic details of the 4-element beamforming transmitter. (Left) Block diagram schematic of the unit transmitter. (Top Right) Schematic of the pseudo-differential multiphase SCPA. (Bottom Right) Schematic of the cascaded unit switching cell. 114 Figure 6.7. 65nm microphotograph. experimental prototype 4-element beamforming TX chip 115 Figure 6.8. Measurement setup for beamforming TX static and dynamic measurements. Figure 6.9. Measured output power and SE versus frequency. 116 Figure 6.10. Measured output power versus code at 1.6 GHz, 1.75 GHz and 1.9 GHz, respectively. . Figure 6.11. Measured SE versus code at 1.6 GHz, 1.75 GHz and 1.9 GHz, respectively. 117 Figure 6.12. Measured ACLR (left) and constellation (right) for a 64 QAM, 15 MHz OFDM signal (LTE) using polar modulation with 1.75 GHz and 1.9 GHz, respectively. 118 Figure 6.13. Measured ACLR (left) and constellation (right) for a 64 QAM, 15 MHz OFDM signal (LTE) using multiphase modulation with 1.75 GHz and 1.9 GHz, respectively. 119 Figure 6.14. Measured beam steering phase error versus steering code for four elements on same die. Figure 6.15. Measured output power versus beam steering phase for four elements on same die. 120 Figure 6.16. Synthesized beam patterns using the measured output phase and power data four elements from a single die compared to ideal synthesized beam phases (clockwise from top left: 0°, 15°, -30°, -45°). 121 Table 6.1. Power loss of different number of phases. All-digital Architecture Maximum Power Loss Average Power Loss Quadrature -3 dB -1.96 dB 8-phase -0.67 dB -0.46 dB 16-phase -0.17 dB -0.11 dB 32-phase -0.04 dB -0.03 dB Digital Polar (Ref.) 0 dB 0 dB 122 Table 6.2. Comparison of prior art. This Work [33] [32] [41] [37] Beamforming Specifications Architecure SCPA with multiphase phaseshifting IDPA with Cartesian PM phaseshifting DSM with Cartesian PM phaseshifting UWB with Vernier delay line MP-SCPA Frequency (GHz) 1.45-2.15 3-7 0.8-1.2 3-5 1.4-2.2 Phase Resolution (°) 0.7 0.35 11.25 1 N/A RMS Resolution (°) 0.32 0.2 0.8-1.2 N/A N/A RMS Pout Error (dB) 0.15 0.2 0.8-1.2 N/A N/A TX Specifications PAE Pout (dBm) 24.4 21.8 N/A N/A 26 Peak SE (%) 24.2 38.2 N/A 7.5 24.9 Modulation 15 MHz, 64QAM, OFDM 25 MHz, 64-QAM 40 MHz, 64-QAM 500 MHz UWB 10 MHz, 64QAM, OFDM Average Pout (dBm) 18.4 14.2 N/A N/A 20.9 Average PAE 14 22 N/A N/A 20.9 EVM ( %) 3.7 4.7 3.5/6.6 N/A 3.5 ACLR (dBc) -30.5/-30.9 N/A <-32 N/A -30.3/-31.7 DPD No Yes N/A N/A Yes General Specifications CMOS Tech. (nm) 65 40 40 130 130 Supply Voltage (V) 1.4/2.8 1.1/1.2 1 1.2 1.5/3 Chip Area (𝒎𝒎𝟐 ) 5 8.6 0.19 7.2 3.8 CHAPTER 7 CONCLUSIONS AND FUTURE WORK Future 5G communications will heavily leverage beamforming and MIMO techniques, owing to the improvement in data transmission capacity. In a TX beamformer, the phase and amplitude of an array of TXs can be arbitrarily adjusted to spatially steer a transmitted beam toward a user, or multiple users. The amplitude and direction of the beam is adjusted by controlling the gain and phase of each TX in the array. In this work, I propose a multiphase interpolating digital power amplifier for TX beamforming. A multiphase controller directly controls a PA, allowing for high phase/gain resolution with reduced loss by performing a vector addition of the beam phase and amplitude. The proposed digital phased array beamforming is implemented in C-2C SAMP-SCPAs. In the previous work, split-array SCPA techniques are introduced and implemented in a prototype SAMP-SCPA in 65nm CMOS. The concept of multiphase signaling is used to leverage the advantages of DPAs while not requiring the wideband phase modulator of polar DPAs or having the high combining loss of quadrature DPAs. SAMP-SCPA achieves similar output power and SE to prior art in digital PAs, while offering reduced OOB noise. The SAMP-SCPA is not just a power amplifier, but a versatile digital transmitter front-end. The transmitter is versatile and linearity can be traded off for output power and efficiency. In addition, the digital phased array can provide more 124 flexibility and its capacity for multiuser beamforming. It allows multiple beams to be formed and directed to an arbitrary number of users. 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