Design and implementation of clocked open core protocol interfaces for intellectual property cores and on-chip network fabric

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Title Design and implementation of clocked open core protocol interfaces for intellectual property cores and on-chip network fabric
Publication Type thesis
School or College College of Engineering
Department Electrical & Computer Engineering
Author Gudla, Raghu Prasad
Date 2011-05
Description This thesis designs, implements, and evaluates modular Open Core Protocol (OCP) interfaces for Intellectual Property (IP) cores and Network-on-Chip (NoC) that re- duces System-On-Chip (SoC) design time and enables research on di erent architectural sequencing control methods. To utilize the NoCs design time optimization feature at the boundaries, a standardized industry socket was required, which can address the SoC shorter time-to-market requirements, design issues, and also the subsequent reuse of developed IP cores. OCP is an open industry standard socket interface speci cation used in this research to enable the IP cores reusability across multiple SoC designs. This research work designs and implements clocked OCP interfaces between IP cores and On-Chip Network Fabric (NoC), in single- and multi- frequency clocked domains. The NoC interfaces between IP cores and on-chip network fabric are implemented using the standard network interface structure. It consists of back-end and front-end submodules corresponding to customized interfaces to IP cores or network fabric and OCP Master and Slave entities, respectively. A generic domain interface (DI) protocol is designed which acts as the bridge between back-end and front-end submodules for synchronization and data ow control. Clocked OCP interfaces are synthesized, placed and routed using IBM's 65nm process technology. The implemented designs are veri ed for OCP compliance using SOLV (Sonics OCP Library for Veri cation). Finally, this thesis reports the performance metrics such as design target frequency of operation, latency, area, energy per transaction, and maximum bandwidth across network on-chip for single- and multifrequency clocked designs.
Type Text
Publisher University of Utah
Subject Average power; Energy per transaction; Maximum bandwidth; Area and latency; Domain interface; Back-ends; Front-ends; IP cores; System-on-chip; Network-on-chip; Open core protocol; RTL development; Logic synthesis; APR and testing; Single-frequency clocked domain; Multifrequency clocked domain
Dissertation Institution University of Utah
Dissertation Name Master of Science
Language eng
Rights Management Copyright © Raghu Prasad Gudla 2011
Format application/pdf
Format Medium application/pdf
Format Extent 9,105,880 bytes
Identifier us-etd3,14979
Source Original in Marriott Library Special Collections QA3.5 2011 .G83
ARK ark:/87278/s6kk9sh9
Setname ir_etd
ID 194488
Reference URL https://collections.lib.utah.edu/ark:/87278/s6kk9sh9
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