Design and integration of high speed relative timed network-on-chip routers

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Title Design and integration of high speed relative timed network-on-chip routers
Publication Type thesis
School or College College of Engineering
Department Electrical & Computer Engineering
Author Takur, Dheeraj singh
Date 2016
Description Integrated circuits often consist of multiple processing elements that are regularly tiled across the two-dimensional surface of a die. This work presents the design and integration of high speed relative timed routers for asynchronous network-on-chip. It researches NoC's efficiency through simplicity by directly translating simple T-router, source-routing, single-flit packet to higher radix routers. This work is intended to study performance and power trade-offs adding higher radix routers, 3D topologies, Virtual Channels, Accurate NoC modeling, and Transmission line communication links. Routers with and without virtual channels are designed and integrated to arrayed communication networks. Furthermore, the work investigates 3D networks with diffusive RC wires and transmission lines on long wrap interconnects.
Type Text
Publisher University of Utah
Subject ASYNCHRONOUS; MESH; NETWORK ON CHIP; NoC; RELATIVE TIME; ROUTER
Dissertation Name Master of Science
Language eng
Rights Management ©Dheeraj singh Takur
Format application/pdf
Format Medium application/pdf
Format Extent 1,263,242 bytes
Identifier etd3/id/4304
ARK ark:/87278/s68p97vd
Setname ir_etd
ID 197849
Reference URL https://collections.lib.utah.edu/ark:/87278/s68p97vd
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