Quantifying the impact of interblock wire-delays on processor performance

As logic delays continue to decrease with smaller process technology, on-chip wire delays are growing exponentially and are expected to increase cross-chip communication latencies to tens of cycles. In this work, we quantify the performance impact of wire-delays in three important contexts: (i) within an aggressive outof- order (OoO) processor pipeline on a two-dimensional (2D) plane, (ii) within a three-dimensional (3D) die-stacked processor and (iii) within coherence communication paths of a chip multiprocessor. We perform a detailed characterization of the loops in a super-scalar pipeline and show that previous attempts to characterize the impact of wire-delays on performance over-estimate the IPC degradation for some loops. We observe that most loops tend to become less critical as more speculation and simple optimizations are introduced, three-dimensional stacking allows dies to be bonded with each other in the vertical dimension enabling further reduction in wire-length. We incorporate the data from the criticality study into a floor-planner that leverages 3D to reduce the lengths of the most critical interblock wires. The overall results argue against leveraging 3D to improve single-core performance and shows that IPC-aware 2D floor-plans perform within an acceptable range of 3D. Coherence operations on multicore architectures necessitate frequent communication over global on-chip wires. Different coherence messages may have varying delay-tolerance levels. We quantify the sensitivity to wire delays for each type of coherence message in an OoO multiprocessor model employing directory-based cache coherence. We observe that OoO processors are able to hide latency in coherence operations adequately and hence there is potential to save considerable power over the interconnect by employing efficient power-optimization strategies.