Symbolic asynchronous hardware protocol verification for compositions with relative timing

This thesis work provides a methodology and a tool fl ow for verifying asynchronous hardware protocols through compositional model checking with symbolic methods. Correct interaction of asynchronous hardware protocols requires veri cation. Per-formance and power of asynchronous hardware circuits and protocols can be vastly improved by modifying them with judicious application of timing constraints. This approach uses relative timing constraints for modeling timed asynchronous hard-ware protocols. This work illustrates the modeling techniques for interleaving and simultaneous compositions with relative timing, which helps in pruning the reachable state space with an overhead of enforcing relative timing constraints. The modeling technique for relative timing does not alter the individual initial protocols. Relative timing constraints are enforced at the interface external to the protocol component. Di erent modeling types are explored for modeling relative timing. Symbolic model checking is performed with properties required for ensuring compositional correctness using the NuSMV engine.