Relative timing based verification and design with delay insensitive signal path modeling with application for field programmable gate arrays

The relative timing (RT) based asynchronous design methodology has been successfully used to create application specific integrated circuit (ASIC) designs that are a process generation ahead of their synchronous counterparts in terms of power, performance and energy. However, while the implementation of RT asynchronous circuits has been dealt with successfully in the ASIC domain, there has been limited exploration of utilizing the design methodology on field programmable gate arrays (FPGAs). This dissertation seeks to address the challenges in implementing RT asynchronous circuits on FPGAs. Relative Timing uses path-based timing constraints to guarantee that a circuit conforms to its behavioral specification. A methodology for the design of glitch free burstmode asynchronous controllers on FPGAs is presented. Path based timing constraints are implement to ensure circuit functionality. A flow for the modeling of the circuit, extraction of relative timing constraints, and implementation of the extracted constraints is presented. Optimizations that enable faster implementation and more robust designs are discussed. The dissertation also presents a framework to evaluate and rank relative timing constraint sets for a given circuit. Multiple constraint sets are possible for a single circuit. The constraint sets are evaluated on the basis of robustness of the constraints and conflicts between constraints in the same set. The methodology is used to optimize the extraction of relative timing constraints. An FPGA architecture capable of relative timing based digital implementations is designed. Modifications are made to a traditional synchronous FPGA architecture to make it asynchronous capable, while retaining its capability as a fully functional synchronous FPGA. A Microprocessor without Interlocked Pipeline Stages (MIPS) design is used to test the FPGA. A performance improvement of 1.7x and a power improvement of 2.3x is achieved. Furthermore, a novel reconfigurable circuit capable of implementing the entire family of 2-phase and 4-phase latch protocols is presented. The circuit is implemented on the International Business Machine Artisan 65nm node and its performance is compared with implementations on a Xilinx Virtex-5 chip that is manufactured on a similar node. A 4x improvement in speed and 2.7x improvement in energy per cycle is achieved.