Low-power operation of microprocessor systems in the presence of process variation

With the scaling of MOSFET dimensions and the performance enhancement features in the MOSFET, semiconductor manufacturing variation has also increased. Because of process variation and other reliability issues, circuits tend to move away from the nominal operating point, therefore degrading the parametric yield of the circuits. To assess the impact of process variations on the parametric yield of integrated circuits, an accurate process variation detection scheme is needed. This dissertation presents a new process variation detection and compensation technique. This technique uses the difference of the rise and fall slew as another metric along with delay in order to determine the magnitude and the relative mismatch between the drive strengths of the NMOS and PMOS devices. The importance of considering both of these metrics is illustrated, and a new slew-rate monitoring circuit is presented for use in measuring the difference of rise and fall slew on the critical path of the circuit. The measurement sensitivity of fabricated slew-rate monitor in a 65nm IBM CMOS technology is 0.11 V/?s with 1089 pF as the output load of the slew-rate monitor.