Design of memory structures for map decoder

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Publication Type honors thesis
School or College College of Engineering
Department Electrical Engineering
Thesis Supervisor Magdy F. Iskander
Honors Advisor/Mentor Laurence P. Sadwick
Creator Hardman, Thomas Martin
Title Design of memory structures for map decoder
Date 1998-08
Year graduated 1998
Description The rapidly growing field of digital communications (telecommunications, video conferencing, the Internet, etc.) has forced engineers to devise new methods for accurately transmitting and receiving digital information. Because signals sent by a transmitter to a receiver are distorted by environmental disturbances (noise), the complete recovery of transmitted information is not a trivial task. One of the tools used to recover digital information is a decoder, which is the implementation of a mathematical algorithm that "makes decisions" about the information bits obtained by a receiver. An example of such an algorithm is the maximum a posteriori (MAP) algorithm, which is used to calculate the probability that a given information bit is "high" or "low" based on the relative probabilities of each of the ways that the bit could have been encoded. To decode a signal with the MAP algorithm, the entire data sequence must be received before a "decision" can be made about the first information bit. This makes implementation of the MAP algorithm memory intensive, and it introduces unnecessary latency into the decoder. One of the traditional solutions to this problem is the sliding window decoder, which requires far less memory to implement, but which also is characterized by slow data throughout. A modification of the traditional sliding window approach will not only reduce the memory requirements of the complete MAP algorithm, but will also provide faster data throughout. A hardware description language (VHDL) was used to implement this; modified approach. The author designed and implemented two memory structures-the BMSM and the Ping Pong-used to shuttle calculation values and provide timing and control to other parts of the decoder. After designing and implementing these memory structures, the author tested them to ensure proper function. The body of this paper provides a detailed description of the design strategy, the individual modules used to implement the overall design of the memory structures, and the testing procedure.
Type Text
Publisher University of Utah
Subject Computer algorithms; Virtual storage (Computer science); Error-correcting codes (Information theory)
Language eng
Rights Management (c) Thomas Martin Hardman
Format Medium application/pdf
ARK ark:/87278/s6ms7wdt
Setname ir_htca
ID 1320451
Reference URL https://collections.lib.utah.edu/ark:/87278/s6ms7wdt
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