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CreatorTitleDescriptionSubjectDate
26 Hibler, Michael J.Notes on thread models in Mach 3.0During the Mach In-Kernel Servers work, we explored two alternate thread models that could be used to support traps to in-kernel servers. In the "migrating threads" model we used, the client's thread temporarily moves into the server's task for the duration of the call. In t h e "thread switching" ...Thread models; In-kernel servers; Thread switching; Mach 3.01993
27 Zhang, LixinReference manual of impulse system callsThis document describes the Im pulse system calls. The Impulse system calls allow user applications to use remapping functionality provided by the Impulse Adaptive Memory System to remap their data structures. Impulse supports several remapping algorithms. User applications choose the desired remapp...Impulse system calls; Remapping functionality; Impulse Adaptive Memory System; Remapping algorithms1999
28 Shirley, Peter S.; Parker, Steven G.Temporally coherent interactive ray tracingAlthough ray tracing has been successfully applied to interactively render large datasets, supersampling pixels will not be practical in interactive applications for some time. Because large datasets tend to have subpixel detail, one-sample-per-pixel ray tracing can produce visually distracting popp...Temporally coherent; interactive ray tracing; large datasets2001
29 Brunvand, Erik L.Translating concurrent programs into delay-insensitive circuitsPrograms written in a subset of occam are automatically translated into delay-insensitive circuits using syntax-directed techniques. The resulting circuits are improved using semantics-preserving circuit-to-circuit transformations. Since each step of the translation process can be proven correct, th...1989
30 Balasubramonian, RajeevA case for increased operating system support in chip multi-processorsWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most com...2005
31 Brunvand, Erik L.A case for increased operating system support in chip multi-processorsWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most com...2005
32 Organick, Elliott I.CASL - A language for automating the implementation of computer architecturesThe computer Architecture Specification Language (CASL), described in this paper, is intended for use by computer architects CASL is a state machine description language especially useful for describing digital systems at the "register transfer" level and designed to meet the needs of the computer a...Computer Architecture Specification Language1979
33 Balasubramonian, RajeevEnergy-efficient processor design using multiple clock domains with dynamic voltage and frequency scalingAs clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processor in which the chip is d...Multiple clock domains; Synchronization; Microarchitecture2002
34 Susarla, Sai R.; Carter, JohnFlexible consistency for wide area peer replicationThe lack of a flexible consistency management solution hinders P2P implementation of applications involving updates, such as read-write file sharing, directory services, online auctions and wide area collaboration. Managing mutable shared data in a P2P setting requires a consistency solution that...Wide area; Peer replication2004-11-18
35 Brunvand, Erik L. ; Gopalakrishnan, GaneshHigh-level asynchronous system design using the ACK frameworkDesigning asynchronous circuits is becoming easier as a number of design styles are making the transition from research projects to real, usable tools. However, designing asynchronous "systems" is still a difficult problem. We define asynchronous systems to be medium to large digital systems whose...2000
36 Carter, John B.Reducing consistency traffic and cache misses in the avalanche multiprocessorFor a parallel architecture to scale effectively, communication latency between processors must be avoided. We have found that the source of a large number of avoidable cache misses is the use of hardwired write-invalidate coherency protocols, which often exhibit high cache miss rates due to exces...Consistency traffic; Cache misses; Parallel architecture; Communication latency1995
37 Panangaden, PrakashAbstract interpretation and indeterminacyWe present a semantic theory that allows us to discuss the semantics of indeterminate operators in a dataflow network. The assumption is made that the language in which the indeterminate operators are written has a construct that allows for the testing of availability of data on input lines. We then...Semantics; Indeterminate operators1984
38 Kessler, Robert R.DPOS: A metalanguage and programming environment for parallel processorsThe complexity and diversity of parallel programming languages and computer architectures hinders programmers in developing programs and greatly limits program portability. All MIMD parallel programming systems, however, address common requirements for process creation, process management, and inte...DPOS; MIMD parallel programming1990
39 Evans, DavidGraphical man/machine communications: June 1971Semi-Annual Technical Report for period 1 January 1971 to 31 May 1971. This document includes a summary of research activities and facilities at the University of Utah under Contract F30602-70-C-0300. Information conveys important research milestones attained during this period by each of the fo...Curved surfaces; Digital waveform processing1971
40 Johnson, Christopher R.Grid-enabling problem solving environments: a case study of SCIRun and NetSolveCombining the functionality of NetSolve, a grid-based middleware solution, with SCIRun, a graphically-based problem solving environment (PSE), yields a platform for creating and executing grid-enabled applications. Using this integrated system, hardware and/or software resources not previously ac...Grid computing; SCIRun; NetSolve; Problem solving environment; Numerical libraries; Parallel programming (Computer science)2001
41 Lindstrom, Gary E.The key node method: a highly-parallel alpha-beta algorithmA new parallel formulation of the alpha-beta algorithm for minimax game tree searching is presented. Its chief characteristic is incremental information sharing among subsearch processes in the form of "provisional" node value communication. Such "eager" communication can offer the double benefit of...Key node method; Alpha-beta algorithm; Minimax; Game tree searching1983
42 Regehr, JohnThe problems you're having may not be the problems you think you're having: results from a latency study of windows NTThis paper is intended to catalyze discussions on two intertwined systems topics. First, it presents early results from a latency study of Windows NT that identifies some specific causes of long thread scheduling latencies, many of which delay the dispatching of runnable threads for tens of millisec...1999-01-01
43 Wright, KristinUsing reliable multicast for caching and collaboration within the world wide webThe World Wide Web has become an important medium for information dissemination. One model for synchronized information dissemination within the Web is webcasting in which data are simultaneously distributed to multiple destinations. The Web's traditional unicast client/server communication model su...caching; collaboration1999
44 Carter, John B.; Davis, Al; Kuramkote, Ravindra; Stoller, Leigh B.Avalanche: A communication and memory architecture for scalable parallel computingAs the gap between processor and memory speeds widens?? system designers will inevitably incorpo rate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance At the same time?? most communication subsystems are permitted access only to main m...Avalanche; Communication architecture; Memory architecture1995
45 Hibler, Michael J.The flask security architecture: system support for diverse security policiesOperating systems must be flexible in their support for security policies, i.e., the operating system must provide sufficient mechanisms for supporting the wide variety of real-world security policies. Systems claiming to provide this support have failed to do so in two ways: they either fail to pro...Flask; Security architecture1998
46 Hibler, Michael J.Interface and execution models in the fluke kernelWe have defined and implemented a new kernel API that makes every exported operation either fully interruptible and restartable, thereby appearing atomic to the user. To achieve interruptibility, all possible states in which a thread may become blocked for a "long" time are completely representable ...Fluke kernel; Interruptibility1998
47 Balasubramonian, RajeevLeveraging 3D technology for improved reliabilityAggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower supply voltages have increased the vulnerability of computer systems towards transient faults. An increase in within-die an...Reliability; Redundant multi-threading, 3D die-stacking; Parameter variation; Soft errors; Dynamic timing errors; Power-efficient microarchitecture; On-chip temperature2007-12
48 Balasubramonian, RajeevPower efficient approaches to redundant multithreadingNoise and radiation-induced soft errors (transient faults) in computer systems have increased significantly over the last few years and are expected to increase even more as we move toward smaller transistor sizes and lower supply voltages. Fault detection and recovery can be achieved through redund...Reliability; Power; Transient faults; Soft errors; Redundant multithreading (RMT); Heterogeneous chip multiprocessors dynamic frequency scaling2007-08
49 Balasubramonian, RajeevPower-efficient approaches to reliabilityRadiation-induced soft errors (transient faults) in computer systems have increased significantly over the last few years and are expected to increase even more as we move towards smaller transistor sizes and lower supply voltages. Fault detection and recovery can be achieved through redundancy. St...Radiation-induced; Soft errors; Transient faults; Redundant thread; Trailing thread; Power consumption2005
50 Evans, JohnA distributed object-oriented graphical programming systemThis report presents the design of a distributed parallel object system (DPOS) and its implementation using a graphical editing interface. DPOS brings together concepts of object-oriented programming and graphical programming with aspects of modern functional languages. Programs are defined as netwo...Distributed parallel object system; DPOS1990
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