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226 A distributed object-oriented graphical programming systemThis report presents the design of a distributed parallel object system (DPOS) and its implementation using a graphical editing interface. DPOS brings together concepts of object-oriented programming and graphical programming with aspects of modern functional languages. Programs are defined as netwo...Distributed parallel object system; DPOS1990
227 Concurrent SchemeThis paper describes an evolution of the Scheme language to support parallelism with tight coupling of control and data. Mechanisms are presented to address the difficult and related problems of mutual exclusion and data sharing which arise in concurrent language systems. The mechanisms are tailored...Concurrent Scheme; Parallelism1990
228 A scheduling strategy for shared memory multiprocessorsAn efficient scheduling strategy for shared memory multiprocessors is described. The rapid dissemination of tasks to available procesors and ready queues is crucial to the performance of any parallel system. Such overheads determine the attainable speedup and performance of the system. Poor techniq...Shared memory multiprocessors1990
229 hopCP: language definition, semantics and examplesWe describe a formalism for high level modeling of hardware based on flow graphs and nonatomic actions called hopCP. A module is the description of a hardware system in hopCP, which contains a flow graph to model the behavioral aspects and ports which represent the communication links. Operations ar...hopCP1990
230 DPOS: A metalanguage and programming environment for parallel processorsThe complexity and diversity of parallel programming languages and computer architectures hinders programmers in developing programs and greatly limits program portability. All MIMD parallel programming systems, however, address common requirements for process creation, process management, and inte...DPOS; MIMD parallel programming1990
231 Interaction with constraints in 3D modelingInteractive geometric modeling is an important part of the industrial product design process. This paper describes how constraints can be used to facilitate the interactive definition of geometric objects and assemblies. We have implemented a geometric modeling system that combines the definition o...Interactive geometric modeling; Industrial product design; Geometric constraints1990
232 From process-oriented functional specifications to efficient asynchronous circuitsA methodology for high-level synthesis and performance optimization of asynchronous circuits is described. A specification language called hopCP which is based on a simple extension to classical flow graphs is introduced. The extension involves the addition of expression actions to a flow graph, to ...Synthesis; Performance optimization1991
233 Hierarchical action refinement: a methodology for compiling asynchronous circuits from a concurrent HDLA hardware specification formalism called hopCP is introduced, hopCP provides an uniform notation t o describe the causal relationships between a set of nonatomic actions which capture the computational, concurrency, control and communication aspects of hardware behavior. A systematic approach to sy...Hierarchical action refinement; Hardware specification formalism; hopCP1991
234 hopCP: A concurrent hardware description languagehopCP is a language for the specification, simulation, and synthesis of hardware systems. hopCP captures the behavior of a hardware system by specifying the causal relationships between actions that the system can perform. No specific timing discipline is implied by a hopCP specification. Hence, hop...hopCP; Hardware systems1991
235 Static analysis techniques for the synthesis of efficient asynchronous circuitsIn the context of deriving asynchronous circuits from high-level descriptions, determining whether two actions are potentially concurrent (overlapped execution) or serial (non-overlapped execution) has several advantages. This knowledge can be utilized to efficiently implement shared variables, sup...Static analysis; Synthesis1991
236 Verification of regular arrays by symbolic simulationMany algorithms have an efficient hardware formulation as a regular array of cells, which can be implemented in VLSI as regular circuit structures. Bit-sliced microprocessors, pattern matching circuits, associative cache memories, Hue-grain systolic arrays, and embedded memory-with-logic structure...Verification; regular arrays; symbolic simulation1991
237 System performance advisor user guideThe usage of the System Performance Advisor (SPA) expert system is described. Documentation of SPA system commands, system variables, diagnostic rules is given. Information on how to run the SPA system is discussed. In addition, an overview of how SPA searches for problems is supplied. The purpose o...System Performance Advisor; SPA; User guide1991
238 Generality Vs. speed of convergence in the cart-pole balancerThis paper compares the speed of convergence to an optimal solution of four controllers for the problem of balancing a pole on a cart. We demonstrate that controllers whose design is tailored specifically to the cart-pole problem (i.e. less general) converge more rapidly to an optimal solution. How...Cart-pole balancer; Generality; Speed of convergence1991
239 Parallel path consistencyFiltering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We ar...Filtering algorithms; Parallel paths; Consistency; Consistent labeling problem; CLP1991
240 A cell set for self-timed design using actel FPGAsAsynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. However, these systems require that suitable self-timed circuit primitives are available for b...Self-timed systems; Actel field programmable gate arrays; FPGA1991
241 A lisp-based occam interpreterThe OCCAM programming language is an implementation of Communicating Sequential Processes and is used in a number of different areas. These areas usually require explicitly describing small-grain paralleslism. OCCAM programs formed by such descriptions can be tested for correctness by executing the...Lisp-based; Occam interpreter1991
242 Transforming disfigured and disoriented areas into routable switchboxesRouting an entire circuit requires partitioning the circuit (routing area) into smaller, localized routing areas. Using non-rectangular, rotated switchbox shapes (and therefore non-manhattan routing layout) has the potential to simplify the partitioning of the circuit into routable areas and to use ...Disfigured areas; Disoriented areas; routable switchboxes1991
243 Using a functional language and graph reduction to program multiprocessor machines or functional control of imperative programsThis paper describes an effective means for programming shared memory multiprocessors whereby a set of sequential activities are linked together for execution in parallel. The glue for this linkage is provided by a functional language implemented via graph reduction and demand evaluation. The full ...shared memory multiprocessors; Programming; functional language; graph reduction; Demand evaluation1991
244 Modularity meets inheritanceWe "unbundle" several roles of classes in existing languages, by providing a suite of operators independently controlling such effects as combination, modification, encapsulation, name resolution, and sharing, all on the single notion of module. All module operators are forms of inheritance. Thus, ...Modularity; Jigsaw computer tool1991
245 Efficient symbolic simulation based verification using the parametric form of boolean expressions (rev.)We present several new techniques to make symbolic simulation based verification efficient. These techniques hinge on the use of the parametric form of a boolean expression (e.g. the parametric form for the boolean expression XQ V -<xi is the equivalent expression 3a b . (XQ = a V 6) A (xi = b), whe...Symbolic simulation; Verification1991
246 Error bounded variable distance offset operator for free from curves and surfacesMost offset approximation algorithms for freeform curves and surfaces may be classified into two main groups. The first approximates the curve using simple primitives such as piecewise arcs and lines and then calculates the (exact) offset operator to this approximation. The second offsets the contro...Error bounded; Freeform curves1991
247 Semantic definition of a subset of the structured query language (SQL)SQL is a relational database definition and manipulation language. Portions of the manipulation language are readily described in terms of relational algebra. The semantics of a subset of the SQL select statement is described. The select statement allows the user to query the database. The select st...1991
248 Switchbox routing by pattern matchingMany good algorithms have been designed that provide good solutions to the wire routing problem in VLSI. Unfortunately, many of these algorithms only consider a small subset of different parameters such as number of layers, routability of layers and technology. We believe that these algorithms can b...Switchbox routing; pattern matching; wire routing problem; VLSI1991
249 A dynamic recursive structure for intelligent inspectionWe suggest a new approach for inspection and reverse engineering applications. In particular we investigate the use of discrete event dynamic systems DEDS to guide and control the active exploration and sensing of mechanical parts for industrial inspection and reverse engineering?? We introduce...Intelligent inspection; Discrete event dynamic systems; DEDS; Industrial inspection; Dynamic recursive structure1992
250 The NSR processor prototypeThe NSR (Non-Synchronous RISC) processor is a general purpose processor structured as a collection of self-timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines. These units correspond to standard synchronous pipeline stages such as Instructi...Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor; NSR1992
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