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| Author | Title | Subject | Date | Publication Type | ||
|---|---|---|---|---|---|---|
| 1 |
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Vij, Vikas S. | Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows | Algorithms; Asynchronous circuits; Methodology; Relative timing; Synchronous CAD tools | 2013-12 | dissertation |
| 2 |
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Xu, Yang | Algorithms for automatic generation of relative timing constraints | Asynchronous circuits; Formal verification; Relative timing | 2011-05 | dissertation |
| 3 |
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Desai, Krishnaji | Symbolic asynchronous hardware protocol verification for compositions with relative timing | BDD; Relative timing; SAT; Symbolic model checking; Timed asynchronous protocol; Verification | 2010 | thesis |
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