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AuthorTitleSubjectDatePublication Type
1 Vij, Vikas S.Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flowsAlgorithms; Asynchronous circuits; Methodology; Relative timing; Synchronous CAD tools2013-12dissertation
2 Xu, YangAlgorithms for automatic generation of relative timing constraintsAsynchronous circuits; Formal verification; Relative timing2011-05dissertation
3 Manoranjan, Jotham VaddaboinaRelative timing based verification and design with delay insensitive signal path modeling with application for field programmable gate arraysApplied sciences; Asynchronous circuits; FPGAs2017dissertation
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