| Title | Date | Type | Setname | ||
|---|---|---|---|---|---|
| 1 |
 |
Dynamic gates with hysteresis and configurable noise tolerance | 2007 | Text | ir_uspace |
| 2 |
 |
Page 200 | dha_uhbr | ||
| 3 |
 |
Page 352 | ir_etd | ||
| 4 |
 |
Page 41 | ir_computersa | ||
| 5 |
 |
Page 40 | ir_computersa | ||
| 6 |
 |
Page 40 | ir_computersa | ||
| 7 |
 |
Page 40 | ir_computersa | ||
| 8 |
 |
Page 18 | ir_computersa | ||
| 9 |
 |
Page 146 | dha_uhbr | ||
| 10 |
 |
Page 71 | dha_uac_wcm | ||
| 11 |
 |
Page 6 | dha_uhbr | ||
| 12 |
 |
Page 91 | ir_etd | ||
| 13 |
 |
Page 201 | dha_uhbr | ||
| 14 |
 |
Page 73 | dha_uhbr | ||
| 15 |
 |
Page 7 | ir_computersa | ||
| 16 |
 |
Floating gate common mode feedback circuit for low noise amplifiers | 2003-01-01 | Text | ir_uspace |
| 17 |
 |
Castle Gate, Utah [03] | 1968; 1969; 1970; 1971; 1972; 1973; 1974 | Image/StillImage | uum_map |
| 18 |
 |
Castle Gate, Utah, on line of D. R. G. R. R. | 1914; 1915; 1916; 1917; 1918; 1919; 1920; 1921; 1922; 1923; 1924 | Image | dha_upc |
| 19 |
 |
Page 99 | ir_etd | ||
| 20 |
 |
Castle Gate, Utah, D. & R. G., R. R. | 1900; 1901; 1902; 1903; 1904; 1905; 1906; 1907; 1908; 1909; 1910; 1911; 1912; 1913; 1914; 1915; 1916; 1917; 1918; 1919; 1920 | Image | dha_upc |
| 21 |
 |
Castle Gate | 1930; 1931; 1932; 1933; 1934; 1935; 1936; 1937; 1938; 1939; 1940; 1941; 1942; 1943; 1944; 1945; 1946; 1947; 1948; 1949 | Image | uum_map_rr |
| 22 |
 |
Page 229 | dha_uhbr | ||
| 23 |
 |
Page 104 | ir_computersa | ||
| 24 |
 |
Automatic addition of reset in asynchronous sequential control circuits | 2014-01-01 | Text | ir_uspace |
| 25 |
 |
Floating-gate PFET-based CMOS programmable analog memory cell array | 2000-01-01 | Text | ir_uspace |