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CreatorTitleDescriptionSubjectDate
1 Myers, Chris J.Technology mapping of timed circuitsAbstract This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the design process to optimi...1995
2 Furse, Cynthia M.Down to the wireAs today's military and commercial aircraft age past their teen years, the many kilometers of wiring buried deep within their structures begin to crack and fray. Once thought to be rare and benign, such faults are found by the hundreds in a typical aircraft. Unlike obvious cracks in a wing or an e...Aging wiring; Wire fault location; Aging wire detection; Smart wire systems2001-01-01
3 Myers, Chris J.Architectural synthesis of timed asynchronous systemsThis paper describes a new method for architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponenti...1999
4 Khan, Faisal HabibCommercial and industrial applications getting ready for direct-current power distributionThis paper describes design trends in several classes of power-electronic appliances that will increase the appeal for distributing dc power in buildings. In the commercial sector information technology (IT) power conversion architectures are moving from multi- to single-voltage supplies, initially...Direct current power distribution; Commercial applications2004-01-01
5 Stevens, KennethAn A-FPGA architecture for relative timing based asynchronous designsThis paper presents an asynchronous FPGA architecture that is capable of implementing relative timing based asynchronous designs. The architecture uses the Xilinx 7-Series architecture as a starting point and proposes modifications that would make it asynchronous design capable while keeping it full...2014-01-01
6 Stevens, KennethLazy transition systems and asynchronous circuit synthesis with relative timing assumptionsThis paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a tr...2002
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