{"responseHeader":{"status":0,"QTime":6,"params":{"q":"{!q.op=AND}id:\"99881\"","hl":"true","hl.simple.post":"","hl.fragsize":"5000","fq":"!embargo_tdt:[NOW TO *]","hl.fl":"ocr_t","hl.method":"unified","wt":"json","hl.simple.pre":""}},"response":{"numFound":1,"start":0,"docs":[{"file_name_t":"Gu-Parallel_Algorithms.pdf","thumb_s":"/f4/0d/f40d2743de4da2acf0142f14f8038f2546aa7ee7.jpg","oldid_t":"compsci 7994","setname_s":"ir_computersa","restricted_i":0,"format_t":"application/pdf","modified_tdt":"2016-05-25T00:00:00Z","file_s":"/f2/2c/f22cc9b03427ea7bf237413d43cc56b1231d59a0.pdf","title_t":"Page 233","ocr_t":"215 cessor arrays. The complete architecture can be globally synchronized or self-time controlled. The parallel mDRA algorithm performed on parallel mDRA architecture is il-lustrated in Figure 6.40. It has optimal time complexity, i.e., O(nm). Meanwhile, its convergence property has been greatly improved. Real algorithm run and simĀulation indicate that this algorithm is many orders faster than the parallel DRA5 algorithm. Three advanced parallel mDRA architectures were designed during 1988 (68]. Some implementation issues for the parallel rnDRA architecture are discussed in the next sections. 6. 7 Wafer-Scale Integration of Parallel DRA Architectures VLSI circuits offer a wonderful computing medium with incredible computing power and permit much spatial parallelism within a 2-dimensional plane, while in any sequential uniprocessor machine only !-dimensional serial computation is possible. In order to map the optimal parallel DRAS and mDRA algorithms onto a VLSI architecture to solve large size engineering problems, one has to deal with the following two critical challenges: (I) 1/0 Problem. 1/0 design in the DRAS and mDRA implementation are important. It may become a bottleneck for the entire system, if we still follow the track of conventional chip level design. (2) Extension to Large Scale Computation. When problem size (n and m) in-creases, or one selects a very large granule size in processor implementation, the complete design has to be implemented on separate chips, thus increasing the per-formance penalties resulting from off-chip communication. This is due mainly to the time required to drive the package pins and also the expense of initializing","id":99881,"created_tdt":"2016-05-25T00:00:00Z","parent_i":99969,"_version_":1679953745579868161}]},"highlighting":{"99881":{"ocr_t":[]}}}