{"responseHeader":{"status":0,"QTime":3,"params":{"q":"{!q.op=AND}id:\"99861\"","hl":"true","hl.simple.post":"","hl.fragsize":"5000","fq":"!embargo_tdt:[NOW TO *]","hl.fl":"ocr_t","hl.method":"unified","wt":"json","hl.simple.pre":""}},"response":{"numFound":1,"start":0,"docs":[{"file_name_t":"Gu-Parallel_Algorithms.pdf","thumb_s":"/6b/14/6b14a23dc82358258c9d6ac817ae04fb3bddc211.jpg","oldid_t":"compsci 7974","setname_s":"ir_computersa","restricted_i":0,"format_t":"application/pdf","modified_tdt":"2016-05-25T00:00:00Z","file_s":"/25/d5/25d5d88269b5575d60953d666c512f01895e4443.pdf","title_t":"Page 213","ocr_t":"195 Table 6.1. Probabilistic Area and Delay Bounds for Some Structures Structures I Area Overhead I Maximum Delay I Linear array in 1-D arrays [58] 8(1) 9(logn) Linear array in 2-D arrays (109] 9(1) 9( v'fOgn) Selector [58] 9(logn) 9(logn) Pairing [58] 0(1) 0(1) Linear array in 2-D array [58] 0(1) 0(1) Square array in 2-D array [58] - 0(~) ... [110] 0( ( loglogn )2) 0( ~loglogn) ... [58] 0(1) 0(~) two linear arrays, etc. Similar bounds are derived by Leighton and Leiserson [109] for linear arrays constructed from 2-dimensional meshes and 2-dimensional meshes extracted from larger 2-dimensional meshes. These results are summarized in Table In the constant time model (see Assumption 6.1 ), this switching algorithm requires an O(nm) area and imposes an 0(1) time wire delay. In practice, comparing the DRA3 architecture against other possible embodiments, it is obvious that there is no extra wiring required. That is, no extra wire delay is really introduced in the DRA3 switching lattice. Switching nodes placed on every cross point on the Interconnection Lattice. and Multiplexer (see Figures 6.26 and 6.28) amplify and pump up the signals passing through them, which shortens the original signal de-lays. Therefore, our 0(1) time delay model (Assumption 6.1) can be employed here without any trouble. In practice, MOSAIC's Series 3000 line of UNIPRO Silicon Circuit Board offers only approximately 9 pico seconds wiring delay per interchip interconnection. According to the statistics collected from several chip implementations, area overhead takes about 4 \"J 7 percent of the total layout area of the 9 0() , 0() , and no stand for the exact, the upper and the lower bounds respectively.","id":99861,"created_tdt":"2016-05-25T00:00:00Z","parent_i":99969,"_version_":1679953745573576706}]},"highlighting":{"99861":{"ocr_t":[]}}}