{"responseHeader":{"status":0,"QTime":5,"params":{"q":"{!q.op=AND}id:\"99797\"","hl":"true","hl.simple.post":"","hl.fragsize":"5000","fq":"!embargo_tdt:[NOW TO *]","hl.fl":"ocr_t","hl.method":"unified","wt":"json","hl.simple.pre":""}},"response":{"numFound":1,"start":0,"docs":[{"file_name_t":"Gu-Parallel_Algorithms.pdf","thumb_s":"/c4/9b/c49b53230b4a7b405c8c772dd736c13b5abf0ff2.jpg","oldid_t":"compsci 7910","setname_s":"ir_computersa","restricted_i":0,"format_t":"application/pdf","modified_tdt":"2016-05-25T00:00:00Z","file_s":"/57/7e/577e8b629ab88832cefc583ecf88c51512042fb9.pdf","title_t":"Page 149","ocr_t":"131 that attempts, using the best technology available today, to achieve the best design insofar as possible. The primitive strategies of designing DRA architectures can best be described by introducing these architectures. An earlier, sequential DRAl system suffers from O(n3m3 ) time complexity, for an n-object and m-label DRA problem, which makes many real-time applications infeasible. By formulating DRA into a parallel computing tree, a parallel, SIMD, hardware DRA2 algorithm was developed. This algorithm was implemented on a DRA2 chip using a multidimensional, virtual treeroot pipelining scheme on ann by m SIMD multiprocessor array. The original time complexity of DRA1 is then reduced to O(n2m2), while the space requirement is divided by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm) [67 ,131,203,204]. Furthermore, a theoretical analysis of the DRA data distribution pattern was undertaken. A highly concurrent, dynamically structured DRA3 algorithm was created. A technique for dynamically configuring an architectural wavefront is used which generates a DRA processor pattern (i.e., a computing structure) and a DRA data distribution pattern (i .e. , a problem structure) simultaneously and leads to an O(n2m) time highly configurable DRA3 architecture [67,62]. Finally, an O(nm) time optimal, parallel DRA5 architecture was designed. It has been used as a hardware search space pruning engine in several parallel consistent labeling architectures. [65]. For problems of practical interest, four to ten orders of magnitude of efficiency improvement can be reached on these DRA machines. The hardware implementation issues of these discrete relaxation architectures are addressed. The first three architectures were designed and prototyped (i .e., implemented) for the same 8-object 8-label DRA problems. The first two systems were implemented using Path Programmable Logic (PPL) integrated circuit design","id":99797,"created_tdt":"2016-05-25T00:00:00Z","parent_i":99969,"_version_":1679953745554702336}]},"highlighting":{"99797":{"ocr_t":[]}}}