{"responseHeader":{"status":0,"QTime":3,"params":{"q":"{!q.op=AND}id:\"97145\"","hl":"true","hl.simple.post":"","hl.fragsize":"5000","fq":"!embargo_tdt:[NOW TO *]","hl.fl":"ocr_t","hl.method":"unified","wt":"json","hl.simple.pre":""}},"response":{"numFound":1,"start":0,"docs":[{"file_name_t":"Chandramouli-Design_Of.pdf","thumb_s":"/b1/53/b153d9942167416d9a03be043973fb22c3375e57.jpg","oldid_t":"compsci 5258","setname_s":"ir_computersa","restricted_i":0,"format_t":"application/pdf","modified_tdt":"2016-04-27T00:00:00Z","file_s":"/69/98/6998a2bcf0ecc14a1aa6e0a724a0de2e1a6e89e1.pdf","title_t":"Page 118","ocr_t":"104 5.5.5 Implementing the Exponent Adder The exponent for the single precision format is eight bits wide and we could use a simple ripple carry adder to do the addition concurrently with the partial product reduction. However, in the case of an overflow we need to increment the exponent by 1. Therefore, the adder could be implemented in the form of a carry select adder with the final output being selected by the overflow bit. Note that care must be taken to subtract the value of bias (in this case 127) to get correctly biased exponents. 5.5.6 Putting It All Together The block diagram of the final carrypropagate/rounding unit is shown in FigĀure 5.9. Most of the blocks are self-explanatory in light of the above discussion. Here, ackl and ack2 are generated by the array part for each iteration. The mdone signal is generated by the array part after every three iterations which causes the carry save result to be latched. This initiates the CPA/rounding phase. Once the carry propagate addition is done the done signal could be delayed by the worst case or dual rail could be used. Also, the done_ack that comes from the outside should be used to clear the various latches. In the block diagram, only a bundled implementation is shown. Only the algorithm for the default rounding mode, i.e., round to nearest/ even has been presented. Now the same algorithm can be extended very easily to handle the other three rounding modes as shown in [34] and they are not reproduced here. 5.5.7 Two-phase to Four-phase Converter Since a precharged adder has been used, conversion from two-phase signalling to four-phase signalling is required. A circuit that does this is shown in Figure 5.10.","id":97145,"created_tdt":"2016-04-27T00:00:00Z","parent_i":97163,"_version_":1642982409198632962}]},"highlighting":{"97145":{"ocr_t":[]}}}