{"responseHeader":{"status":0,"QTime":7,"params":{"q":"{!q.op=AND}id:\"97057\"","hl":"true","hl.simple.post":"","hl.fragsize":"5000","fq":"!embargo_tdt:[NOW TO *]","hl.fl":"ocr_t","hl.method":"unified","wt":"json","hl.simple.pre":""}},"response":{"numFound":1,"start":0,"docs":[{"file_name_t":"Chandramouli-Design_Of.pdf","thumb_s":"/76/76/7676e5b0d92979448920f84d5218ae1da733e13d.jpg","oldid_t":"compsci 5170","setname_s":"ir_computersa","restricted_i":0,"format_t":"application/pdf","modified_tdt":"2016-04-27T00:00:00Z","file_s":"/ec/eb/eceb2fdc2c70054737d3e5cd1bd65c909db30121.pdf","title_t":"Page 30","ocr_t":"16 multiplier (including routing) which is then extrapolated for the entire multiplier. Thus these figures are only approximations. The latencies on the other hand have been obtained by looking at the number of Carry Save Adder ( CSA) delays in the critical path. The latency is then expressed in terms of CSA delays. 2.2 Basics of Binary Multiplication The binary counterpart of the pencil and paper algorithm for decimal numbers is shown in Figure 2.1 for the eight bit case. Here X is the multiplicand and Y is the multiplier. Each term of the form XiYi (represented as a dot in the fig) is called a partial product (PP) term. A row of such terms is called a PP row and the number of terms in a row is determined by the number of bits in the multiplicand. The entire collection of PP terms is called the PP array or PP matrix. The height of the PP matrix is equal to the height of the tallest column in this matrix which in turn is equal to the number of bits in the multiplier. With a multiplicand of m bits and a multiplier of n bits, we get a product of m + n bits. For fast multiplication, we try to reduce all the columns of PP terms in parallel. Typically, then rows of PPs are reduced to final two rows of sum and carry bits which are then summed by a fast Carry Propagate Adder (CPA). In most cases, the PPs are represented in the carry save form to avoid ripple carrys during partial product reduction. Sometimes other representations such as the redundant binary are also used [15]. However, in this research only architectures using the more popular carry save representation were investigated. The architectures described in this chapter all differ in the way they reduce the rows of PPs to the final two rows of sum and carry bits which are then summed by a fast CPA. 2.3 IEEE Single Precision Format The IEEE single precision format has a total word size of 32 bits of which 23 are for the mantissa, 8 for the exponent and 1 bit for the sign. The standard uses","id":97057,"created_tdt":"2016-04-27T00:00:00Z","parent_i":97163,"_version_":1642982409172418562}]},"highlighting":{"97057":{"ocr_t":[]}}}