NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

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Publication Type pre-print
School or College College of Engineering
Department Computing, School of
Creator Balasubramonian, Rajeev
Other Author Pugsley, Seth H.; Jestes, Jeffrey; Zhang, Huihui; Srinivasan, Vijayalakshmi; Buyuktosunoglu, Alper; Davis, Al; Li, Feifei
Title NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
Date 2014-01-01
Description While Processing-in-Memory has been investigated for decades, it has not been embraced commercially. A number of emerging technologies have renewed interest in this topic. In particular, the emergence of 3D stacking and the imminent release of Micron's Hybrid Memory Cube device have made it more practical to move computation near memory. However, the literature is missing a detailed analysis of a killer application that can leverage a Near Data Computing (NDC) architecture. This paper focuses on in-memory MapReduce workloads that are commercially important and are especially suitable for NDC because of their embarrassing parallelism and largely localized memory accesses. The NDC architecture incorporates several simple processing cores on a separate, non-memory die in a 3D-stacked memory package; these cores can perform Map operations with efficient memory access and without hitting the bandwidth wall. This paper describes and evaluates a number of key elements necessary in realizing efficient NDC operation: (i) low-EPI cores, (ii) long daisy chains of memory devices, (iii) the dynamic activation of cores and SerDes links. Compared to a baseline that is heavily optimized for MapReduce execution, the NDC design yields up to 15X reduction in execution time and 18X reduction in system energy.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 190
Last Page 200
Language eng
Bibliographic Citation Pugsley, S.H., Jestes, J., Zhang, H., Balasubramonian, R., Srinivasan, V., Buyuktosunoglu, A., Davis, A., & Li, F. (2014). NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads. ISPASS 2014 - IEEE International Symposium on Performance Analysis of Systems and Software, 6844483, 190-200.
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Format Medium application/pdf
Format Extent 843,312 bytes
Identifier uspace,18872
ARK ark:/87278/s6cz6h8n
Setname ir_uspace
Date Created 2014-08-20
Date Modified 2021-05-06
ID 712654
Reference URL https://collections.lib.utah.edu/ark:/87278/s6cz6h8n
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