Automatic addition of reset in asynchronous sequential control circuits

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Publication Type pre-print
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Stevens, Kenneth
Other Author Vij, Vikas S.
Title Automatic addition of reset in asynchronous sequential control circuits
Date 2014-01-01
Description Asynchronous finite state machines (AFSMs) usually require initialization to place them in a desired starting state. This normally occurs by toggling a reset signal upon power-up. This paper presents an algorithm to automatically generate power-up reset circuitry thus adding reset to an AFSM after technology mapping. This approach is independent of design methodology since it is applied to a gate netlist. The algorithm ensures all combinational cycles and primary outputs in the circuit are initialized. Options exist in reset generation to minimize the power or performance impact on the AFSM. Results are reported for applying this algorithm to designs of varying size and complexity.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 374
Last Page 379
Language eng
Bibliographic Citation Vij, V. S., & Stevens, K. S. (2013). Automatic addition of reset in asynchronous sequential control circuits. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 6673312, 374-9.
Rights Management (c) 2014 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 301,782 bytes
Identifier uspace,18679
ARK ark:/87278/s6fb8c11
Setname ir_uspace
Date Created 2014-05-19
Date Modified 2021-05-06
ID 712551
Reference URL https://collections.lib.utah.edu/ark:/87278/s6fb8c11
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