Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device

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Publication Type pre-print
School or College College of Engineering
Department Computing, School of
Creator Balasubramonian, Rajeev
Other Author Shevgoor, Manjunath; Kim, Jung-Sik; Chatterjee, Niladrish; Davis, Al; Udipi, Aniruddha N.
Title Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
Date 2013-01-01
Description Many of the pins on a modern chip are used for power delivery. If fewer pins were used to supply the same current, the wires and pins used for power delivery would have to carry larger currents over longer distances. This results in an "IR-drop" problem, where some of the voltage is dropped across the long resistive wires making up the power delivery network, and the eventual circuits experience fluctuations in their supplied voltage. The same problem also manifests if the pin count is the same, but the current draw is higher. IR-drop can be especially problematic in 3D DRAM devices because (i) low cost (few pins and TSVs) is a high priority, (ii) 3D-stacking increases current draw within the package without providing proportionate room for more pins, and (iii) TSVs add to the resistance of the power delivery net-work. This paper is the first to characterize the relationship be- tween the power delivery network and the maximum sup ported activity in a 3D-stacked DRAM memory device. The design of the power delivery network determines if some banks can handle less activity than others. It also deter-mines the combinations of bank activities that are permissible. Both of these attributes can feed into architectural policies. For example, if some banks can handle more activities than others, the architecture benefits by placing data from high-priority threads or data from frequently accessed pages into those banks. The memory controller can also derive higher performance if it schedules requests to specific combinations of banks that do not violate the IR-drop constraint.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Issue 198
First Page 209
Language eng
Bibliographic Citation Shevgoor, M., Kim, J.-S., Chatterjee, N., Balasubramonian, R., Davis, A., & Udipi, A. N. (2013). Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device. MICRO 2013 - Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 198-209.
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Format Medium application/pdf
Format Extent 829,974 bytes
Identifier uspace,18437
ARK ark:/87278/s6hm8jfv
Setname ir_uspace
Date Created 2014-03-11
Date Modified 2014-03-11
ID 711699
Reference URL https://collections.lib.utah.edu/ark:/87278/s6hm8jfv
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