Path-programmable logic

Path-Programmable Logic (PPL) is a structured IC design methodology under development at the University of Utah. PPL employs a sea-of-wires approach to design. In PPL, design is done entirely using cells for both functionality and interconnect. PPL cells may have modifiers that change either their connections or functionality. Wires in the PPL design plane are segmentable at any cell boundary. PPL is implemented as a set of cell libraries (NMOS, CMOS, and GaAs) and a suite of tools that permit the designer to create, modify, simulate and check PPL circuit designs and to generate mask data for them. PPL exhibits little or no area penalty with respect to full custom densities while permitting system design to be done more rapidly than with gate arrays or standard cells. PPL may be implemented as a sea-of-gates gate array to provide fast turnaround.