CA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoder

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Publication Type Journal Article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Stevens, Kenneth
Other Author Roncken, Marly; Pendurkar, Rajesh; Rotem, Shai; Chaudhuri, Parimal Pal
Title CA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoder
Date 2000
Description This paper presents a case study in low-cost noninvasive Built-In Self Test (BIST) for RAPPID, a largescale 120,000-transistor asynchronous version of the Pentium® Pro Instruction Length Decoder, which runs at 3.6 GHz. RAPPID uses a synchronous 0.25 micron CMOS library for static and domino logic, and has no Design-for-Test hooks other than some debug features. We explore the use of Cellular Automata (CA) for on-chip test pattern generation and response evaluation. More specifically, we look for fast ways to tune the CA-BIST to the RAPPID design, rather than using pseudo-random testing. The metric for tuning the CA-BIST pattern generation is based on an abstract hardware description model of the instruction length decoder, which is independent of implementation details, and hence also independent of the asynchronous circuit style. Our CA-BI ST solution uses a novel bootstrap procedure for generating the test patterns, which give complete coverage for this metric, and cover 94% of the testable stuck-at faults for the actual design at switch level. Analysis of the undetected and untestable faults shows that the same fault effects can be expected for a similar clocked circuit. This is encouraging evidence that testability is no excuse to avoid asynchronous design techniques in addition to high-performance synchronous solutions.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 62
Last Page 72
Language eng
Bibliographic Citation Roncken, M., Stevens, K. S., Pendurkar, R., Rotem, S., & Chaudhuri, P. P. (2000). CA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoder. Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC-2000), 62-72. April.
Rights Management (c) 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 159,550 bytes
Identifier ir-main,15298
ARK ark:/87278/s6rf6cn5
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 707249
Reference URL https://collections.lib.utah.edu/ark:/87278/s6rf6cn5
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