A partial scan methodology for testing self-timed circuits

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Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Brunvand, Erik L.
Other Author Khoche, Ajay
Title A partial scan methodology for testing self-timed circuits
Date 1995
Description This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 283
Last Page 289
Language eng
Bibliographic Citation Khoche, A., & Bruncand, E. L. (1995). A partial-scan methodology for testing self-timed circuits in 13th IEEE VLSI Test Symposium, 283-9. April.
Relation is Part of ARPANET
Rights Management (c) 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 727,612 bytes
Identifier ir-main,15754
ARK ark:/87278/s6280s63
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 706970
Reference URL https://collections.lib.utah.edu/ark:/87278/s6280s63