Performance analysis and optimization of asynchronous circuits

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Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Gopalakrishnan, Ganesh
Other Author Kudva, Prabhakar; Brunvand, Erik
Title Performance analysis and optimization of asynchronous circuits
Date 1994
Description Asynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VLSI designs. However, there are very few analysis techniques or tools available for estimating the performance of asynchronous circuits. In this paper we adapt the theory of Generalized Timed Petri-nets (GTPN) for analyzing and comparing a wide variety of asynchronous circuits, ranging from purely control-oriented circuits such as cross-bar arbiters to large asynchronous systems with data dependent control such as asynchronous processors. Experiments with the GTPN analyzer are found to track the observed performance of actual asynchronous circuits, thereby offering empirical evidence towards the soundness of the modeling approach. Our main contribution is in demonstrating how a quantitative design methodology for asynchronous circuits can be developed based on Timed Petri-nets.
Type Text
Publisher University of Utah
First Page 1
Last Page 21
Subject Asynchronous circuits; Performance analysis; Optimization; VLSI circuits
Subject LCSH Asynchronous circuits; Performance -- Evaluation; Integrated circuits -- Very large scale integration
Language eng
Bibliographic Citation Kudva, P.; Gopalakrishnan, G., & Brunvand, E. (1994). Performance analysis and optimization of asynchronous circuits. 1-21. UUCS-94-015.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 6,751,500 bytes
Identifier ir-main,16305
ARK ark:/87278/s6dz0svm
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2015-04-24
ID 706324
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