The NSR processor

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Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Brunvand, Erik L.
Title The NSR processor
Date 1993
Description The NSR (Non-Synchronous RISC) processor is a general-purpose computer structured (IS U collection of self-timed blocks that operate concurrently and communicate over bundled data channels in the style of micropipelines [3, 16]. These blocks correspond to standard synchronous pipeline stages such us Instruction Fetch, Instruction Decode, Execute, Memory and register File, but each operates concurrently as a separate self-timed process. In addition to being internally self-timed, the units are decoupled through self-timed FIFO queues between each of the units which allows U high degree of overlap in instruction execution. Branches, jumps, and memory accesses are also decoupled through the use of additional FIFO queues which can hide the execution latency of these instructions. A prototype implementation of the NSR processor has been constructed using Actel FPGAs (Field Programmable Gate Arrays).
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 428
Last Page 435
Language eng
Bibliographic Citation Brunvand, E. L. (1993). The NSR processor. In 26th Hawaiian International Conference on System Sciences, 428-35. Jan.
Rights Management (c) 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 717,197 bytes
Identifier ir-main,15771
ARK ark:/87278/s6cn7ndc
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2012-06-13
ID 706188
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