High level optimizations in compiling process descriptions to asynchronous circuits

Asynchronous/'Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this paper, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatically synthesize asynchronous circuits from descriptions in our concurrent programming language, hopCP. We outline some of the high level communication abstractions available in hopCP. We illustrate how these abstractions are realized in the asynchronous circuits generated by SHILPA. We then present a series of examples that present many of the high level optimization strategies used by SHILPA. Some of these optimizations aim to speed up the generated circuits by avoiding un-necessary waiting. Others synthesize components that are much easier to realize in a variety of technologies. We also discuss some of the tradeoffs possible between optimizations and timing constraints.