A systolic array implementation of discrete relaxation algorithm

Discrete Relaxation techniques have proven useful in solving a wide range of problems in digital signal processing, artificial intelligence, machine vision, and VLSI engineering, etc. A conventional hardware design for an 8-label 8-object Discrete Relaxation Algorithm (DRA) requires three 4K memory blocks and the maximum execution time of over seconds and minutes, which makes such a DRA hardware implementation infeasible. A highly parallel systolic array for the computation of an 8-label 8-object DRA problem has been developed. This realization eliminates the 12K memory requirement and performs DRA computation at the worst case in microseconds. The circuit requires about 6,382 transistors. Major design issues and chip descriptions are described in this paper.