Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Tinker, Peter |
Title |
Managing large address spaces effectively on the Butterfly |
Date |
1987 |
Description |
The BBN Butterfly? Parallel Processor is a commercially-available multiprocessor which uses a memory management strategy based on a segmentation of the available memory. Using all of the memory of the machine efficiently is difficult because of the need to change the memory mapping dynamically. This difficulty discourages the use of the Butterfly for applications requiring a large address space. This paper presents a scheme for using all of the Butterfly's memory with minimal impact through dynamic re-mapping of memory. Called SAR-smashing, it is appropriate for applications which require access to widely-scattered memory locations throughout a potentially large address space. The method was developed to support an OR-parallel logic programming system for the Butterfly which requires large stack data areas. Benchmark timing results for the memory access strategy are presented. |
Type |
Text |
Publisher |
University of Utah |
First Page |
1 |
Last Page |
10 |
Subject |
BBN Butterfly Parallel Processor; Large address spaces |
Subject LCSH |
Parallel processing (Electronic computers) |
Language |
eng |
Bibliographic Citation |
Tinker, P. (1987). Managing large address spaces effectively on the butterfly. 1-10. UUCS-87-012. |
Series |
University of Utah Computer Science Technical Report |
Rights Management |
©University of Utah |
Format Medium |
application/pdf |
Format Extent |
4,154,193 bytes |
Identifier |
ir-main,16331 |
ARK |
ark:/87278/s6sn0tfz |
Setname |
ir_uspace |
ID |
705853 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6sn0tfz |