Design and validation of a simultaneous multi-threaded DLX processor

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Jacobson, Hans
Title Design and validation of a simultaneous multi-threaded DLX processor
Date 1999
Description Modern day computer systems rely on two forms of parallelism to achieve high performance, parallelism between individual instructions of a program (ILP) and parallelism between individual threads (TLP). Superscalar processors exploit ILP by issuing several instructions per clock, and multiprocessors (MP) exploit TLP by running different threads in parallel on different processors. A fundamental imitation of these approaches to exploit parallelism is that processor resources are statically partitioned. If TLP is low, processors in a MP system will be idle, and if ILP is low, issue slots in a superscalar processor will be wasted. As a consequence, the hardware cannot adapt to changing levels of ILP and TLP and resource utilization tend to be low. Since resource utilization is low there is potential to achieve higher performance if somehow useful instructions could be found to fill up the wasted issue slots. This paper explores a method called simultaneous multithreading (SMT) that addresses the utilization problem by letting multiple threads compete for the resources of a single processor each clock cycle thus increasing the potential ILP available.
Type Text
Publisher University of Utah
First Page 1
Last Page 11
Subject DLX processor; Validation
Language eng
Bibliographic Citation Jacobson, H. (1999). Design and validation of a simultaneous multi-threaded DLX processor. 1-11. UUCS-99-013.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 3,492,503 bytes
Identifier ir-main,15962
ARK ark:/87278/s61n8jm3
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2015-04-23
ID 705736
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