Leveraging 3D technology for improved reliability

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Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Balasubramonian, Rajeev
Other Author Madan, Niti
Title Leveraging 3D technology for improved reliability
Date 2007-12
Description Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower supply voltages have increased the vulnerability of computer systems towards transient faults. An increase in within-die and die-to-die parameter variations has also led to a greater number of dynamic timing errors. A potential solution to mitigate the impact of such errors is redundancy via an in-order checker processor. Emerging 3D performance as well as reduced power consumption because of shorter on-chip wires. In this paper, we leverage the "snap-on" functionality provided by 3D integration and propose implementing the redundant checker processor on a second die. This allows manufacturers to easily create a family of "reliable processors" without significantly impacting the cost or performance for customers that care less about reliability. We comprehensively evaluate design choices for this second die, including the effects of L2 cache organization, deep pipelining, and frequency. An interesting feature made possible by 3D integration is the incorporation of heterogeneous process technologies within a single chip.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 223
Last Page 235
DOI 10.1109/MICRO.2007.31
Subject Reliability; Redundant multi-threading, 3D die-stacking; Parameter variation; Soft errors; Dynamic timing errors; Power-efficient microarchitecture; On-chip temperature
Subject LCSH Computer storage devices; Computer systems -- Reliability; Microprocessors -- Reliability
Language eng
Conference Title 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007); ; Chicago, IL, USA
Bibliographic Citation Madan, N., & Balasubramonian, R. (2007). Leveraging 3D technology for improved reliability. Proceedings of the Annual International Symposium on Microarchitecture, MICRO, 4408258, 223-35.
Rights Management (c) 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. http://dx.doi.org/10.1109/MICRO.2007.31
Format Medium application/pdf
Format Extent 490,747 bytes
Identifier ir-main,11472
ARK ark:/87278/s6rb7p15
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2012-06-13
ID 705541
Reference URL https://collections.lib.utah.edu/ark:/87278/s6rb7p15
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