PPL 1.2mu gallium arsenide cell set

The purpose of this note is to describe the 1.2/i gallium arsenide PPL cell set - not only what is included, but design decisions made along the way. The first section is an overview of the Umitations imposed by the use of gallium arsenide technology, the next section describes the trade-offs in designing the GaAs cell set, and the third section is a description of the cell set in its current form. The last section gives some design guidelines for using this cell set. The appendix is a short reference guide, including cell schematics. This cell set uses the Vitesse 1.2^ process, and Direct-Coupled FET Logic (DCFL) gates. Enhancement and depletion transistors are provided, with depletion devices generally connected as passive pull-ups and enhancement devices as active pull-downs. The reader interested in the details of gallium arsenide technology is referred to the excellent book by Long and Butner[l] or to any of the proceedings from the annual IEEE Symposium on Gallium Arsenide.